Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
View Patent ↗An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.
1. A method for accessing a memory device that supports both synchronous and asynchronous modes of operation, and comprises a memory interface and a plurality of storage arrays, wherein at least one storage array of the plurality of storage arrays operates within a different clock domain than another storage array of the plurality of storage arrays, the method comprising:
receiving an address of data to be accessed, and either a clock signal or an asynchronous control signal, the address being within the at least one storage array;
latching the address when operating in the asynchronous mode, the address being latched responsive to the asynchronous control signal;
registering the address when operating in the synchronous mode, the registered address to be supplied in synchronization with the clock signal;
using an address multiplexer to selectively forward the latched address or the registered address, depending on the mode selected, to access the at least one storage array, access to the at least one storage array during the synchronous mode being controlled by a different clock signal than the clock signal supplied to the memory interface circuit; and
generating a signal, which prevents a change that is made to the data while the data is being accessed from propagating out of the memory device while the data is being accessed.
2. The method as recited in claim 1 , further comprising receiving a mode selection signal indicating whether the data should be accessed in synchronous or asynchronous mode.
3. The method as recited in claim 2 , wherein if the mode selection signal indicates that the data should be accessed in the synchronous mode, the signal is generated through synchronizing the clock signal to a high speed clock signal.
4. The method as recited in claim 2 , wherein if the mode selection signal indicates that the data should be accessed in the asynchronous mode, the signal is generated through synchronizing the asynchronous control signal to a high speed clock signal.
5. The method as recited in claim 2 , wherein the signal comprises a pulse, which (i) allows the data to propagate out of the memory device when the pulse is asserted, and (ii) prevents the change to the data from propagating out of the memory device when the pulse is deasserted.
6. The method as recited in claim 5 , wherein for each access of the at least one storage array, the pulse is asserted only for about one clock cycle of a high speed clock signal, and deasserted thereafter.
7. The method as recited in claim 2 , wherein if the mode selection signal indicates that the data should be accessed in the asynchronous mode, the method further comprises:
generating a control signal by synchronizing an asynchronous control signal to a high speed clock signal; and
supplying the generated control signal to a latch, which is coupled for receiving the data before it is forwarded out of the memory device.
8. The method as recited in claim 7 , wherein the generating of the control signal and the supplying of the control signal prevent the data from entering a metastable state, the control signal to cause an opening of the latch after a few clock cycles of the high speed clock signal and a closing the latch in synchronization with the high speed clock signal.
9. A memory device comprising:
a plurality of storage arrays; and
a memory interface circuit configured to:
operate in a select one of two available modes, including a synchronous mode and an asynchronous mode,
receive an address of data to be accessed, the address being located within a storage array of the plurality of storage arrays, and
receive a clock signal when operating in the synchronous mode, and an asynchronous control signal when operating in the asynchronous mode, the memory interface circuit including:
an address interface logic comprising:
an address latch configured to latch the address when operating in the asynchronous mode, the address being latched responsive to the asynchronous control signal,
an address register configured to register the address when operating in the synchronous mode, the registered address to be supplied in synchronization with the clock signal, and
an address multiplexer configured to selectively forward the latched address or the registered address, depending on the mode selected, to access the storage array, access to the storage array during the synchronous mode being controlled by a different clock signal than the clock signal supplied to the memory interface circuit.
10. The memory device of claim 1 , wherein the memory interface circuit is configured to access the plurality of storage arrays in the synchronous mode during a first time period and to access the plurality of storage arrays in the asynchronous mode during a second time period, the second time period being distinct from the first time period.
11. The memory device of claim 1 , wherein the memory interface circuit is configured to access the storage array of the plurality of storage arrays in the synchronous mode and another storage array of the plurality of storage arrays in the asynchronous mode.
12. The memory device of claim 1 , wherein storage elements within the plurality of storage arrays are selected from a group comprising Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), registers and latches.
13. The memory device of claim 1 , wherein the memory interface circuit includes data interface logic comprising:
a data latch configured to latch output data from the-storage array when operating in the asynchronous mode, wherein the output data is latched through an internal control signal generated within the memory interface circuit;
a data register configured to register output data from the storage array when operating in the synchronous mode, wherein the registered data is supplied in synchronization with the clock signal; and
a data multiplexer configured to selectively forward the latched output data or the registered output data, depending on the mode selected, out of the memory device.
14. The memory device of claim 13 , wherein the memory interface circuit comprises control logic, which ensures that the output data is stable, regardless of the mode selected.
15. The memory device of claim 14 , wherein during the asynchronous mode, the control logic synchronizes the asynchronous control signal to a high speed clocking signal to generate the internal control signal, which is supplied to the data latch to latch the output data to the data multiplexer.
16. The memory device of claim 15 , wherein the control logic comprises:
a control signal multiplexer configured to selectively forward the clock signal or the asynchronous control signal, depending on the mode selected, to a chain of registers all but one of the chain of registers having an output coupled to an input of a succeeding register in the chain to propagate the clock signal or the asynchronous control signal, depending on the mode selected, which is selectively forwarded by the control signal multiplexer, in synchronization with the high speed clocking signal; and
a first logic gate coupled to the outputs of a last two registers in the chain and configured to generate the internal control signal.
17. The memory device of claim 16 , wherein during synchronous and asynchronous modes, the control logic uses the high speed clocking signal and either the clock signal or the asynchronous control signal, depending on the mode selected, to generate a pulse that prevents data updates within the storage array from propagating to the data multiplexer when the pulse is asserted.
18. The memory device of claim 17 , wherein the control logic further comprises:
a second logic gate coupled to the outputs of the last two registers in the chain and configured to generate the pulse; and
at least one multiplexer coupled to the storage array and at least one register coupled to the data interface logic, wherein the at least one multiplexer is configured to:
pass the data from the storage array to the at least one register, if the pulse is deasserted, and
prevent the data from the at least one storage array from passing to the at least one register, if the pulse is asserted.