IP Library Patent Application 11956439
Patent Application
App. No. 11/956,439

SIMULATION METHOD, SIMULATION SYSTEM, AND METHOD OF CORRECTING MASK PATTERN

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Quick Facts
Patent No.
US None
App. No.
11/956,439
Abstract

A simulation system has an entry acceptance unit, a calculation unit, and a decision unit. The entry acceptance unit accepts an entry of measured dimension of the transfer pattern, the calculation unit includes an electric field vector calculation unit, a flare electric field vector calculation unit and a light intensity calculation unit. The electric field vector calculation unit calculates triaxial vector components of electric field at every position, the flare electric field vector calculation unit calculates a flare electric field vector based on polarization ratio of an exposure tool, and based on tentative horizontal ratio and tentative vertical ratio on the wafer surface for every position, the light intensity calculation unit calculates light intensity by adding the electric field vector and the flare electric field vector so as to calculate sum of squares of the triaxial components.

Claims (28)

1 . A simulation method acquiring, by simulation, information on a transfer pattern realizable on a wafer as a result of photolithographic transfer of a mask pattern of a predetermined mask, comprising:

accepting an entry of measured dimension of said transfer pattern;

calculating an electric field vector for every predetermined position in a plane coordinate defined on the surface of said wafer;

calculating a flare electric field vector ascribable to said mask pattern for said every predetermined position;

adding said flare electric field vector to said electric field vector, and obtaining sum of squares of their triaxial vector components, to thereby calculate a light intensity distribution;

assuming a threshold value of light intensity observed for the edges at paired two points specifying calculated dimension of said transfer pattern in the simulation as an unknown constant, and determining, by regressive calculation, said threshold value so as to minimize difference between said calculated dimension and said measured dimension under said light intensity.

2 . The simulation method as claimed in claim 1 ,

wherein said predetermined mask is a phase shift mask, and

in said calculating a flare electric field vector ascribable to said mask pattern, a convolution integral of a mask function having a value of +1 for the 0-phase opening region, a value of −1 for the π-phase opening region, and a value of 0 for the shadowing region of the mask pattern, and Gaussian function having a tentative length of diffusion, is calculated as a first primitive flare, and said first primitive flare is then multiplied respectively by ratio of polarization in each of two orthogonal directions on a plane in parallel with the wafer, to thereby define a first primitive flare vector having the calculated products as the in-plane bidirectional components;

a convolution integral of a mask function having a value of +1 both for the 0-phase opening region and the π-phase opening region of the mask pattern, and Gaussian function having a tentative length of diffusion, is calculated as a second primitive flare vector normal to the wafer; and

said flare electric field vector is defined as a three-dimensional vector based on a combination of said first primitive flare vector multiplied by a tentative horizontal ratio and said second primitive flare vector multiplied by a tentative vertical ratio.

3 . The simulation method as claimed in claim 1 ,

wherein said predetermined mask is a binary mask, and

in said calculating a flare electric field vector ascribable to said mask pattern, a convolution integral of a mask function having a value of 1 for the opening region, and a value of 0 for the shadowing region of the mask pattern, and Gaussian function having a tentative length of diffusion, is calculated as a first primitive flare, and said first primitive flare is then multiplied respectively by ratio of polarization in each of two orthogonal directions on a plane in parallel with the wafer, to thereby define a first primitive flare vector having the calculated products as the in-plane bidirectional components;

said first primitive flare per se is defined as a second primitive flare vector normal to the wafer;

said flare electric field vector is defined as a three-dimensional vector based on a combination of said first primitive flare vector multiplied by a tentative horizontal ratio and said second primitive flare vector multiplied by a tentative vertical ratio.

4 . A method of correcting a mask pattern correcting said mask pattern using a lithographic model obtainable by the simulation method described in claim 1 .

5 . A simulation system acquiring, by simulation, information on a transfer pattern realizable on a wafer as a result of photolithographic transfer of a mask pattern of a predetermined mask, comprising:

a unit of accepting an entry of measured dimension of said transfer pattern;

a unit of calculating an electric field vector for every predetermined position in a plane coordinate defined on the surface of said wafer;

a unit of calculating a flare electric field vector ascribable to said mask pattern for said every predetermined position;

a unit of adding said flare electric field vector to said electric field vector, and obtaining sum of squares of their triaxial vector components, to thereby calculate a light intensity distribution; and

a unit of assuming a threshold value of light intensity observed for the edges at paired two points specifying calculated dimension of said transfer pattern in the simulation as an unknown constant, and determining, by regressive calculation, said threshold value so as to minimize difference between said calculated dimension and said measured dimension under said light intensity.

6 . A photomask having a corrected mask pattern obtainable by the method of correcting a mask pattern described in claim 4 .

7 . A method of manufacturing a semiconductor device comprising:

forming a resist film on a substrate;

forming a pattern in said resist film by light exposure through said photomask described in claim 6 , and development; and

processing said substrate using said resist film having said pattern transferred thereto.

Assignments (2)
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2007
From: KAWAKAMI, YUKIYA
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020246/0751 →