ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE
In one or more embodiments, address translation is performed over a dedicated serial bus between a non-volatile memory controller and a memory device that is external from the non-volatile memory device. The memory controller accesses memory address translation data in the external memory device to determine a physical address that corresponds to a logical memory address. The controller can then use the physical memory address to generate memory signals for the non-volatile memory array.
1 . An address translation system comprising:
a non-volatile memory device comprising a memory controller and a memory array; and
an external memory device, separate from the non-volatile memory device, for storing address translation data accessible by the memory controller over a dedicated serial data bus.
2 . The address translation system of claim 1 wherein the address translation data comprises a table comprised of logical memory addresses and their corresponding physical memory addresses in the non-volatile memory device.
3 . The address translation system of claim 1 wherein the memory array is comprised of a NAND architecture.
4 . The address translation system of claim 1 wherein the external memory device is a DRAM.
5 . The address translation system of claim 1 and further comprising a volatile memory interface coupled to the external memory device for enabling access to the external memory device by an external controller.
6 . The address translation system of claim 1 and further comprising a memory controller interface coupled to the memory controller for enabling access to the memory controller by an external controller.
7 . An address translation system for translating between a logical address and a physical address, the system comprising:
a NAND flash memory device comprising a memory controller coupled to a NAND non-volatile memory array;
an external volatile memory device that is separate from the NAND flash memory device and stores address translation information accessible by the memory controller; and
a dedicated serial data bus connected between the memory controller and the external volatile memory device to enable the memory controller to access the address translation information.
8 . The address translation system of claim 7 and further comprising a DRAM interface coupled to the external volatile memory device and a NAND controller interface coupled to the NAND flash memory device.
9 . The address translation system of claim 7 wherein the memory controller is adapted to generate a range of logical addresses corresponding to redundant memory columns in the memory array that replace defective memory columns.
10 . The address translation system of claim 9 wherein the memory controller is further adapted to access the external volatile memory device over the dedicated serial data bus to retrieve physical memory addresses that correspond to the range of logical addresses corresponding to redundant memory columns.
11 . The address translation system of claim 8 wherein the DRAM interface is comprised of one of a double-data rate interface or a low-power synchronous DRAM interface.
12 . The address translation system of claim 8 wherein the NAND controller interface is comprised of one of a Secure Digital interface, a MultiMediaCard interface, or a SATA interface.
13 . A method for memory address translation comprising:
a non-volatile memory device memory controller accessing with a logical memory address, over a dedicated serial bus, an address translation table in a volatile memory device external from the non-volatile memory device;
the memory controller retrieving a physical memory address, corresponding to the logical memory address, from the translation table; and
the memory controller performing a memory operation on a non-volatile memory array of the non-volatile memory device at least partially in response to the physical memory address.
14 . The method of claim 13 and further including receiving the logical address.
15 . The method of claim 13 and further including the memory controller generating the logical address in response to defective memory columns.
16 . The method of claim 13 wherein the memory operation is received by the memory controller and the memory operation comprises the logical memory address.
17 . The method of claim 13 wherein the memory operation comprises one of a read operation comprising a logical read address or a write operation comprising a logical write address.
18 . A memory system comprising:
a processor for controlling operation of the memory system and generating memory signals; and
a non-volatile memory device coupled to the processor and operating at least partially in response to the memory signals, the memory device comprising:
a non-volatile memory array coupled to a memory controller, the memory controller coupled to the processor through a memory controller interface; and
a DRAM coupled to the memory controller over a dedicated serial bus that connects only the DRAM and the memory controller, the DRAM comprising data for translating between a logical memory address and a physical memory address.
19 . The system of claim 18 wherein the non-volatile memory device is one of a NAND flash memory device or a NOR flash memory device.
20 . The system of claim 18 wherein the memory controller is adapted to access the data for translating over the dedicated serial bus in order to map a received logical memory address to a physical memory address in the non-volatile memory array.
21 . The system of claim 18 wherein the dedicated serial bus is a high speed bus operating at approximately 1 Gb/s.
22 . A method for memory address translation comprising:
a non-volatile memory device memory controller determining logical memory addresses for columns of a memory array that are defective;
the memory controller accessing address mapping data with the logical memory addresses, over a dedicated serial bus, from a volatile memory device external from the non-volatile memory device; and
the memory controller determining, from the address mapping data, physical memory addresses corresponding to the logical memory addresses.
23 . The method of claim 22 and further including the memory controller using the physical memory addresses in generating memory control signals.
24 . The method of claim 22 wherein the address mapping data comprises a logical memory address range with a corresponding physical address range.
25 . The method of claim 22 wherein the columns of the memory array are comprised of NAND series strings of memory cells.