IP Library Granted Patent US 7,867,786
Granted Patent B2
US 7,867,786 · App. 11/958,826 · Granted Jan 11, 2011

Ferroelectric layer with domains stabilized by strain

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Quick Facts
Patent No.
US 7,867,786
App. No.
11/958,826
Granted
Jan 11, 2011
Kind
B2
Abstract

The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer; cooling the substrate to room temperature; and inducing a compressive strain in the ferroelectric layer.

Claims (16)

1. A method of stabilizing domains within a ferroelectric material layer, comprising:

providing a silicon substrate;

forming an underlying layer over said silicon substrate;

heating said silicon substrate to a deposition temperature in a range of 450-900° C.;

epitaxially forming a ferroelectric layer over said underlying layer, said ferroelectric layer having a thickness below a critical thickness, said underlying layer having a smaller lattice constant than said ferroelectric layer, wherein the lattice constants are mismatched by 3.5% to 7.5% and the mismatch in lattice constants cause compressive strain to the layer of ferroelectric material; and

cooling said substrate to room temperature to room temperature to stabilize the domains by applying an in-plane elastic compressive strain in the ferroelectric layer at room temperature.

2. The method of claim 1 wherein said underlying layer comprises a bottom electrode layer of SRO.

3. The method of claim 1 , wherein said domain has a size smaller than 20 nm.

4. A method of stabilizing domains within a ferroelectric material layer, comprising:

providing an underlying layer comprising a silicon substrate;

heating said underlying layer to a deposition temperature in a range of 450-900° C.;

forming a superlattice over the underlying layer at the deposition temperature by epitaxially forming a first layer of a ferroelectric material with a thickness below the critical thickness and then forming alternating layers of a high dielectric constant material and the ferroelectric material, wherein at least the high dielectric constant material has a smaller lattice constant than said ferroelectric material; and

cooling said underlying layer to room temperature to stabilize the domains by applying an in-plane elastic compressive strain in the alternating layers of ferroelectric material at room temperature.

5. The method of claim 4 wherein said underlying layer comprises a bottom electrode layer having a smaller lattice constant than the ferroelectric material is disposed over the silicon substrate, and wherein the first layer of ferroelectric material is lattice mismatched with the bottom electrode layer by 7.5% and 12%.

6. The method of claim 4 wherein said domain has a size smaller than 20 nm.

7. The method of claim 4 , wherein the underlying layer comprises a bottom electrode of SRO.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS INCORRECTLY LISTED (REMOVE 17236651, 17411919, 17483279, 17558001) PREVIOUSLY RECORDED ON REEL 72293 FRAME 842. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2026
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 075695/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 072293/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2009
From: MA, QING; WANG, LI-PENG; RAO, VALLURI
To: INTEL CORPORATION
Reel/Frame 023278/0747 →