Polysilicon dummy wafers and process used therewith
View Patent ↗Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 μm without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
1. A nitride deposition process having a cycle of deposition, comprising
disposing monocrystalline silicon production wafers on some slots of a support tower,
disposing at least one polycrystalline non-production wafer on other slots of the support tower,
in a furnace in which the support tower is disposed, depositing silicon nitride on the production and non-production wafers by chemical vapor deposition; and
repeating the cycle of deposition with different production wafers and the same non-production wafer;
wherein the repeating step continues until silicon nitride is deposited on the same non-production wafer to a thickness of at least 1 micron.
2. The process of claim 1 , wherein the thickness is at least 2 microns.
3. The process of claim 1 , wherein the tower is a silicon tower.
4. The process of claim 1 , wherein the non-production wafer has a thickness in the range of 0.725 to 2 mm.
5. The process of claim 1 , wherein the non-production wafer has both principal sides roughened.
6. The process of claim 5 , wherein both principal sides have sub-surface damage extending at least 25 μm from the principal sides.
7. The process of claim 1 , wherein the polycrystalline non-production wafer comprises a polysilicon member of polysilicon having a substantially randomly oriented crystallography.
8. The process of claim 1 , wherein the polycrystalline non-production wafer comprises CVD-source CZ polysilicon.
9. The process of claim 1 , wherein a diameter of both the production and non-production wafers is a common diameter chosen from 150, 200, 300, and 450 mm.
10. A method of fabricating a non-production wafer, comprising:
cutting a wafer from a polycrystalline silicon ingot;
oxidizing the wafer; and
processing the wafer so that it contains sub-surface damage on both sides thereof at the completion of processing, wherein the sub-surface damage includes cracks and crevices and extends to a depth from both said sides of at least 25 microns.
11. The method of claim 10 , wherein the wafer comprises polysilicon having a substantially randomly oriented crystallography.
12. The method of claim 10 , wherein the wafer comprises CVD-source CZ polysilicon.
13. The method of claim 10 , further comprising pulling the ingot from a silicon melt using a polysilicon seed.
14. The method of claim 10 , further comprising:
growing a silicon rod by chemical vapor deposition; and
cutting the polysilicon seed from the silicon rod.