Semiconductor device and method for manufacturing the same
A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure.
1. A semiconductor device of a NAND memory structure, comprising:
an insulating layer;
a channel structure disposed above the insulating layer, the channel structure comprising:
a channel bridge, connecting between two platforms, wherein a bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions, wherein the two platforms and the plurality of separated doping regions are used as source/drain regions of the NAND memory structure;
an insulating structure wrapping around the channel bridge; and
a plurality of gates located adjacent to the doping regions and wrapping around the insulating structure.
2. The semiconductor device according to claim 1 , wherein a width of the channel bridge is smaller than a width of each of the two platforms.
3. The semiconductor device according to claim 1 , further comprising two supporting pillars disposed on the insulating layer, wherein a material of the two supporting pillars is silicon nitride.
4. The semiconductor device according to claim 1 , wherein the channel bridge has a first surface, a second surface, a third surface and a fourth surface, and the insulating structure wraps around the first to fourth surfaces.
5. The semiconductor device according to claim 4 , wherein the plurality of gates are disposed above the first to fourth surfaces.
6. The semiconductor device according to claim 1 , wherein the insulating structure is an oxide layer.
7. The semiconductor device according to claim 1 , wherein the insulating structure comprises:
a blocking layer; and
a charge storage layer disposed adjacent to the blocking layer.
8. The semiconductor device according to claim 7 , wherein the insulating structure further comprises a tunneling dielectric layer disposed adjacent to the charge storage layer.
9. The semiconductor device according to claim 8 , wherein the tunneling dielectric layer further comprises an ONO layer or an OSO layer.
10. The semiconductor device according to claim 3 , further comprising:
a second insulating layer covering the insulating layer, the two supporting pillars, the channel structure, the insulating structure and the plurality of gates;
two second supporting pillars protruding from the second insulating layer;
a second channel structure, which comprises:
two second platforms respectively disposed on the two second supporting pillars; and
a second channel bridge connecting the two second platforms, wherein a bottom of the second channel bridge is separated from the second insulating layer by a second distance;
a second insulating structure wrapping around the second channel bridge; and
a second gate wrapping around the second insulating structure.