Digital circuits and methods for testing a digital circuit

1. A digital circuit comprising:

a first plurality of storage elements; and

a second plurality of storage elements;

the digital circuit being operable in a first operation mode and in a second operation mode;

wherein, in the first operation mode, the storage elements of the second plurality of storage elements are connected in series to receive and store test data and are disconnected from the storage elements of the first plurality of storage elements, and wherein the first plurality of storage elements receive and transfer signal data within the digital circuit, and

wherein, in the second operation mode, each storage element of the first plurality of storage elements is connected with a corresponding storage element of the second plurality of storage elements, such that each of the second plurality of storage elements is adapted to transmit the test data stored in a respective storage element of the second plurality of storage elements to the corresponding storage element of the first plurality of storage elements, and each of the first plurality of storage elements is adapted to transmit the signal data stored in a respective storage element of the first plurality of storage elements to the corresponding storage element of the second plurality of storage elements.

2. The digital circuit of claim 1 , further comprising:

a data input; and

a data output;

wherein, in the first operation mode, one storage element of the second plurality of storage elements is connected to the data input and a further storage element of the second plurality of storage elements is connected to the data output.

3. The digital circuit of claim 2 , wherein, in the first operation mode, test data is sequentially loaded into storage elements of the second plurality of storage elements via the data input.

4. The digital circuit of claim 1 further comprising a data compressor and a data decompressor.

5. An integrated circuit comprising:

a first plurality of storage elements;

a second plurality of storage elements;

a third plurality of storage elements; and

a fourth plurality of storage elements;

the integrated circuit being operable in a first operation mode and in a second operation mode;

wherein in the first operation mode, the first plurality of storage elements and the second plurality of storage elements receive and transfer signal data within the integrated circuit, and wherein the third plurality of storage elements and the fourth plurality of storage elements are connected in series with one another and receive and store test data while being disconnected from the first and second pluralities of storage elements,

wherein in the second operation mode, each storage element of the first plurality of storage elements is connected to a corresponding storage element of the third plurality of storage elements such that each of the third plurality of storage elements is adapted to transmit the test data stored in a respective storage element of the third plurality of storage elements to the corresponding storage element of the first plurality of storage elements, and each of the first plurality of storage elements is adapted to transmit the signal data stored in a respective storage element of the first plurality of storage elements to the corresponding storage element of the third plurality of storage elements, and each storage element of the second plurality of storage elements is connected to a corresponding storage element of the fourth plurality of storage elements such that each of the fourth plurality of storage elements is adapted to transmit the test data stored in a respective storage element of the fourth plurality of storage elements to the corresponding storage element of the second plurality of storage elements, and each of the second plurality of storage elements is adapted to transmit the signal data stored, in a respective storage element of the second plurality of storage elements to the corresponding storage element of the fourth plurality of storage elements.

6. The integrated circuit of claim 5 , further comprising:

a data input; and

a data output;

wherein, in the first operation mode, one storage element of the third plurality of storage elements is connected to the data input and one storage element of the fourth plurality of storage elements is connected to the data output such that all storage elements of the third plurality and fourth plurality of storage elements are connected in series between the data input and the data output.

7. The integrated circuit of claim 6 , wherein, in the first operation mode, test data is sequentially loaded into storage elements of the third and the fourth plurality of storage elements via the data input.

8. The digital circuit of claim 5 further comprising a data compressor and a data decompressor.

9. A method for testing a digital circuit comprising:

operating a first plurality of storage elements for receiving and transferring signal data within the digital circuit while simultaneously loading and storing test data into a second plurality of storage elements;

pausing the receiving and transferring of signal data by the first plurality of storage elements;

connecting each storage element of the first plurality of storage elements with a corresponding storage element of the second plurality of storage elements, such that each of the second plurality of storage elements transmits the test data stored in a respective storage element of the second plurality of storage elements to the corresponding storage element of the first plurality of storage elements, and each of the first plurality of storage elements transmits the signal data stored in a respective storage element of the first plurality of storage elements to the corresponding storage element of the second plurality of storage elements; and

operating the first plurality of storage elements with test data as the signal data within the digital circuit to process the test data.

10. The method of claim 9 further comprising:

pausing again the receiving and transferring of signal data by the first plurality of storage elements within the digital circuit; and

connecting each storage element of the first plurality of storage elements with the corresponding storage element of the second plurality of storage elements such that each of the second plurality of storage elements transmits the previously transferred signal data stored in a respective storage element of the second plurality of storage elements to the corresponding storage element of the first plurality of storage elements, and each of the first plurality of storage elements transmits the processed test data stored in a respective storage element of the first plurality of storage elements to the corresponding storage element of the second plurality of storage elements.

11. A method for testing a digital circuit comprising:

providing a first operation mode in which test data is loaded into and stored in a second plurality of storage elements while a first plurality of storage elements receives and transfers signal data within the digital circuit; and

further providing a second operation mode, in which each storage element of the first plurality of storage elements is connected with a corresponding storage element of the second, plurality of storage elements, such that each of the second plurality of storage elements transmits the test data stored in a respective storage element of the second plurality of storage elements to the corresponding storage element of the first plurality of storage elements, and each of the first plurality of storage elements transmits the signal data stored in a respective storage element of the first plurality of storage elements to the corresponding storage element of the second plurality of storage elements.

12. The method of claim 11 , wherein in the signal data contents of the first plurality of storage elements represents a state of the digital circuit.