PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF
Phase change memory devices and fabrication methods thereof. A phase change memory device includes an array of phase change memory cells. Each phase change memory cell includes a selecting transistor disposed on a substrate. An upright electrode structure is electrically connected to the selecting transistor. An upright phase change memory layer is stacked on the upright electrode structure with a contact area therebetween, wherein the contact area serves as the location where phase transition takes place.
1 . A phase change memory device, comprising:
a current controlling element disposed on a substrate;
an upright electrode structure electrically connected to the current controlling element; and
a first upright phase change memory layer stacked on the upright electrode structure with a first contact spot therebetween, wherein the first contact spot serves as a phase transition location of a first phase change memory cell.
2 . The phase change memory device as claimed in claim 1 , wherein the upright electrode structure is a conductive wall structure.
3 . The phase change memory device as claimed in claim 1 , wherein the first upright phase change memory layer is a single wall structure.
4 . The phase change memory device as claimed in claim 1 , wherein the upright electrode structure and the first upright phase change memory layer are uprightly crossed, wherein the upright electrode structure and the first upright phase change memory layer are intersected vertically or non-vertically.
5 . The phase change memory device as claimed in claim 2 , wherein the upright electrode structure comprises a high Tm (melting point) conductive material comprising transition metals, rare earth metals, or alloys thereof, nitrides thereof, carbides thereof, or nitro-carbides thereof.
6 . The phase change memory device as claimed in claim 3 , wherein the first upright phase change memory layer comprises phase change memory materials by controlling the status of the generated phase thereof for memory.
7 . The phase change memory device as claimed in claim 6 , wherein the phase change memory materials comprise group III, group IV, group V, group VI metals, or alloys thereof.
8 . The phase change memory device as claimed in claim 1 , wherein the current controlling element is a transistor element.
9 . The phase change memory device as claimed in claim 1 , further comprising a second upright phase change memory layer stacked on the upright electrode structure with a second contact spot therebetween, wherein the second contact spot serves as a phase transition location of a second phase change memory cell.
10 . The phase change memory device as claimed in claim 9 , wherein the second upright phase change memory layer is a single wall structure.
11 . The phase change memory device as claimed in claim 9 , wherein the upright electrode structure and the second upright phase change memory layer are uprightly crossed, wherein the upright electrode structure and the second upright phase change memory layer are intersected vertically or non-vertically.
12 . The phase change memory device as claimed in claim 10 , wherein the second upright phase change memory layer is made of phase change memory materials by controlling the status of the generated phase thereof for memory.
13 . The phase change memory device as claimed in claim 12 , wherein the phase change memory materials comprise group III, group IV, group V, group VI metals, or alloys thereof.
14 . The phase change memory device as claimed in claim 9 , wherein the first and the second upright phase change memory layers are separately connected to two different conductive lines, wherein each conductive line corresponds to a bit line of the phase change memory device.
15 . The phase change memory device as claimed in claim 1 , further comprising:
a plurality of the first phase change memory cells arranged in an array corresponding to a plurality of current controlling elements on the substrate;
a plurality of word lines connecting each current controlling element in series along a first direction; and
a plurality of bit lines connecting each first upright phase change memory layer in series along a second direction,
wherein the first and the second directions are substantially crossed at right angles.
16 . The phase change memory device as claimed in claim 9 , further comprising:
a plurality of the first phase change memory cells and a plurality of the second phase change memory cells arranged in an array corresponding to a plurality of current controlling elements on the substrate;
a plurality of word lines connecting each current controlling element in series along a first direction;
a plurality of first bit lines connecting each first upright phase change memory layer in series along a second direction; and
a plurality of second bit lines connecting each second upright phase change memory layer in series along the second direction,
wherein the first and the second directions are substantially crossed at right angles.
17 . The phase change memory device as claimed in claim 16 , wherein the plurality of current controlling elements are arranged in an array comprising a first set of transistor sub-arrays and a second set of transistor sub-arrays.
18 . The phase change memory device as claimed in claim 17 , wherein the first set of transistor sub-arrays and the second set of transistor sub-arrays are configured as a (½, ½) translation symmetry.
19 . A method for fabricating a phase change memory device, comprising:
providing a substrate with a current controlling element thereon;
forming an upright electrode structure on the substrate electrically connected to the current controlling element; and
forming a first upright phase change memory layer and a second phase change layer on the upright electrode structure.
20 . The method as claimed in claim 19 , wherein the current controlling element is a transistor element.
21 . The method as claimed in claim 19 , wherein the substrate comprises a first dielectric layer and a conductive plug in the first dielectric layer, wherein the conductive plug electrically connects to the current controlling element and the upright electrode structure.
22 . The method as claimed in claim 19 , wherein formation of the upright electrode structure comprises:
forming a second dielectric layer on the first dielectric layer;
patterning the second dielectric layer to create a square opening exposing the conductive plug;
conformably depositing a first conductive layer on the second dielectric layer and the square opening;
depositing a third dielectric layer on the first conductive layer filling in the square opening: and
planarizing the third dielectric layer and the first conductive layer until exposing the second dielectric layer thereby creating a conductive wall structure.
23 . The method as claimed in claim 22 , wherein the first conductive layer comprises a high Tm (melting point) conductive material comprising transition metals, rare earth metals, or alloys thereof, nitrides thereof, carbides thereof, or nitro-carbides thereof.
24 . The method as claimed in claim 19 , wherein formation of a first upright phase change memory layer and a second upright phase change memory layer comprises:
forming a fourth dielectric layer on the third dielectric layer;
patterning the fourth dielectric layer to create a square island structure;
conformably depositing a second conductive layer on the fourth dielectric layer and the third dielectric layer;
anisotropically etching the second conductive layer to create spacers on the square island structure; and
insulating one parallel pair of the spacer walls in a second direction and not insulating the other parallel pair of the spacer walls in a first direction to serve as a first upright phase change layer and a second upright phase change memory layer.
25 . The method as claimed in claim 24 , wherein the first upright phase change layer and the second upright phase change memory layer are made of phase change memory materials by controlling the status of the generated phase thereof for memory.
26 . The method as claimed in claim 25 , wherein the phase change memory materials comprise group III, group IV, group V, group VI metals, or alloys thereof.
27 . The method as claimed in claim 24 , wherein insulating one parallel pair of the spacer walls in a second direction comprises ion-implanting oxygen or nitrogen ions into the parallel pair of spacer walls in the second direction.
28 . The method as claimed in claim 19 , further comprising forming a first bit line connecting the first upright phase change memory layer along the second direction, and forming a second bit line connecting to the second upright phase change memory layer.
29 . The method as claimed in claim 28 , wherein formation of the first and the second bit lines comprises:
depositing a fifth dielectric layer on the fourth dielectric layer and planarizing the fifth dielectric layer;
etching the fifth dielectric layer to create a first trench and a second trench along the second direction, thereby exposing the first and the second upright phase change memory layers;
depositing a third metal layer on the fifth dielectric layer and filling the first trench and the second trench; and
etching the third conductive layer, thereby creating the first and the second bit lines.
30 . The method as claimed in claim 22 , wherein formation of a first upright phase change memory layer and a second upright phase change memory layer comprises:
forming a fourth dielectric layer on the third dielectric layer;
patterning the fourth dielectric layer to create a stripe island structure along the second direction;
forming a fifth dielectric layer on the third and the fourth dielectric layers and planarizing the fifth dielectric layer;
forming a clad metal layer on the fifth dielectric layer;
patterning the clad metal layer and the fifth dielectric layer to create a square island structure;
conformably depositing a second conductive layer on the clad metal layer and the fourth dielectric layer; and
anisotropically etching the second conductive layer to create spacers on the square island structure;
wherein the pair of spacer walls of the second conductive layer in the second direction are insulated from the upright electrode structure by the stripe island structure, and the pair of spacer walls of the second conductive layer in the first direction serve as a first upright phase change memory layer and a second upright phase change memory layer.
31 . The method as claimed in claim 30 , wherein the first upright phase change memory layer and the second upright phase change memory layer are made of phase change memory materials by controlling the status of the generated phase thereof for memory.
32 . The method as claimed in claim 30 , wherein the phase change memory materials comprise group III, group IV, group V, group VI metals, or alloys thereof.
33 . The method as claimed in claim 30 , further comprising forming a first bit line connecting to the first upright phase change memory layer along the second direction, and forming a second bit line connecting to the second upright phase change memory layer.
34 . The method as claimed in claim 33 , wherein formation of the first and the second bit lines comprises:
depositing a sixth dielectric layer on the fifth dielectric layer and planarizing the sixth dielectric layer;
etching the sixth dielectric layer to create a plurality of contact windows exposing the clad metal layer;
depositing a third conductive layer on the sixth dielectric layer and filling the plurality of contact windows, thereby creating a plurality of contact plugs; and
etching the third conductive layer along the second direction to create a plurality of bit lines.
35 . A method for fabricating a phase change memory device, comprising:
providing a substrate with a plurality of current controlling elements arranged in an array and a plurality of word lines connecting to the current controlling elements in series;
forming an upright electrode structure corresponding to each current controlling element on the substrate and electrically connecting to the current controlling element; and
forming a first upright phase change memory layer on the upright electrode structure with a first contact spot therebetween, wherein the first contact spot serves as a first phase change memory cell; and
forming a second upright phase change memory layer on the upright electrode structure with a second contact spot therebetween, wherein the second contact spot serves as a second phase change memory cell, wherein the first phase change memory cell is in parallel with the second phase change memory cell.
36 . The method as claimed in claim 35 , wherein the plurality of current controlling elements are arranged in an array comprising a first set of transistor sub-arrays and a second set of transistor sub-arrays.
37 . The method as claimed in claim 36 , wherein the first set of transistor sub-arrays and the second set of transistor sub-arrays are configured as a (½, ½) translation symmetry.