Low couple effect bit-line voltage generator

1. A bit-line voltage generator, comprising:

a discharge enhanced bias source; and

a switch unit, comprising:

a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage;

a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor;

a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and

a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground,

wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and

the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

2. The bit-line voltage generator as claimed in claim 1 , wherein the discharge enhanced bias source comprises:

an operational amplifier having a noninverting input terminal receiving a reference voltage;

a first diode having an anode connected to an output terminal of the operational amplifier;

a second diode having an anode connected to a cathode of the first diode;

a current source having an input terminal connected to a cathode of the second diode, and an output terminal connected to ground;

a pull low transistor having a gate connected to the input terminal of the current source, and a source connected to the output terminal of the current source;

a pull high transistor having a gate connected to an output terminal of the operational amplifier, a drain receiving to the voltage, and a source connected to a drain of the pull low transistor;

a first resistor having a first terminal connected to the source of the pull high transistor, and a second terminal connected to an inverting input terminal of the operational amplifier; and

a second resistor having a first terminal connected to the inverting input terminal of the operational amplifier, and a second terminal connected to ground.

3. The bit-line voltage generator as claimed in claim 2 , wherein the first diode, the second diode, the current source, the pull high transistor and the pull low transistor constitutes a class AB output stage.

4. The bit-line voltage generator as claimed in claim 2 , wherein the source of the pull high transistor is connected to the gate of the clamp transistor.

5. The bit-line voltage generator as claimed in claim 1 , wherein the discharge enhanced bias source comprises:

a current source having an output terminal connected to ground;

a first transistor having a source connected to an input terminal of the current source;

a second transistor having a gate receiving a reference voltage, and a source connected to an input terminal of the current source;

a third transistor having a gate connected to a source thereof, a drain receiving the voltage, and the source connected to a drain of the first transistor;

a fourth transistor having a gate connected to a source thereof, a drain receiving the voltage, and the source connected to a drain of the second transistor;

a fifth transistor having a gate connected to the gate of the third transistor, and a drain receiving the voltage;

a sixth transistor having a gate connected to a drain thereof, the drain connected to a source of the fifth transistor, and a source connected to ground;

a pull high transistor having a gate connected to the gate of the fourth transistor, and a drain receiving the voltage;

a pull low transistor having a gate connected to the gate of the sixth transistor, a drain connected to a source of the pull high transistor, and a source connected to ground;

a first resistor having a first terminal connected to a source of the pull high transistor, and a second terminal connected to a gate of the first transistor; and

a second resistor having a first terminal connected to the second terminal of the first resistor, and a second terminal connected to ground.

6. The bit-line voltage generator as claimed in claim 5 , wherein the source of the pull high transistor is connected to the gate of the clamp transistor.

7. The bit-line voltage generator as claimed in claim 1 , wherein the discharge enhanced bias source comprises:

a current source having an input terminal receiving the voltage;

a first transistor having a gate receiving a reference voltage, and a drain connected to an output terminal of the current source;

a second transistor having a drain connected to the output terminal of the current source;

a third transistor having a drain connected to a source of the first transistor, and a source connected to ground;

a fourth transistor having a gate connected to a gate of the third transistor, a drain connected to a source of the second transistor, and a source connected to ground;

a fifth transistor having a gate connected to a source thereof, and a drain receiving the voltage;

a sixth transistor having a gate connected to the gate of the third transistor, a drain connected to the source of the fifth transistor, and a source connected to ground;

a pull high transistor having a gate connected to the gate of the fifth transistor, and a drain receiving the voltage;

a pull low transistor having a gate connected to the drain of the third transistor, a drain connected to a source of the pull high transistor, and a source connected to ground;

a coupling capacitor connected between the gate and the drain of the pull low transistor;

a first resistor having a first terminal connected to the source of the pull high transistor, and a second terminal connected to a gate of the second transistor; and

a second resistor having a first terminal connected to the second terminal of the first resistor, and a second terminal connected to ground.

8. The bit-line voltage generator as claimed in claim 7 , wherein the source of the pull high transistor is connected to the gate of the clamp transistor.

9. The bit-line voltage generator as claimed in claim 1 , wherein the source of the switch transistor is connected to a bit-line of the memory array.

10. A switch unit, comprising:

a first transistor having a source, a gate connected to a discharge enhanced bias source, and a drain receiving a voltage;

a second transistor having a gate receiving a control signal, a drain connected to the source of the first transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the first transistor;

a resistor having a first terminal connected to the drain of the second transistor, and a second terminal connected to ground; and

a capacitor having a first terminal connected to the drain of the second transistor, and a second terminal connected to ground,

wherein a charge in the parasitic capacitor, when the second transistor is turned on, is almost identical to that when the second transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

11. The switch unit as claimed in claim 10 , wherein the source of the second transistor is connected to a bit-line of the memory array.

12. A bit-line voltage generator, comprising:

a discharge enhanced bias source; and

a switch unit having a circuit unit and a parasitic capacitor coupled between the circuit unit and the discharge enhanced bias source, and connected between the discharged enhanced bias source and a memory array,

wherein the circuit unit makes a charge in the parasitic capacitor, when the switch transistor is turned on, almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

13. The bit-line voltage generator as claimed in claim 12 , wherein the switch unit is connected to a bit-line of the memory array.