Nonvolatile semiconductor storage device having a low resistance write-bit-line and a low capacitance read-bit-line pair
A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data from the memory cell. In addition, a write bit-line is arranged in a direction perpendicular to the word-line to write data to the memory cell. The read bit-line pair includes a true and a complementary read bit-line. One of the true and complementary read bit-lines is connected to the memory cell connected to an even-numbered word-line. The other one is connected to the memory cell connected to an odd-numbered word-line.
1. A non-volatile semiconductor storage device comprising:
a memory cell array comprising memory cells disposed in a matrix;
a plurality of word-lines arranged in the memory cell array, the word-lines being for selecting a memory cell in a row direction;
a read bit-line pair arranged in a direction perpendicular to the word-line, the read bit-line pair being for reading data from the memory cell;
a write bit-line arranged in the direction perpendicular to the word-line, the write bit-line being for writing data to the memory cell; and
a sense amplifier amplifying a potential difference generated across the read bit-line pair,
the read bit-line pair comprising a true and a complementary read bit-line, one of the true and complementary read bit-lines being connected to a memory cell connected to an even-numbered word-line, and the other one being connected to a memory cell connected to an odd-numbered word-line.
2. The non-volatile semiconductor storage device according to claim 1 , wherein
the memory cell comprises an antifuse device, the antifuse device having a first end connected to a write power supply, the antifuse device storing data depending on whether a dielectric breakdown occurs due to a voltage applied across the first end and a second end of the antifuse device.
3. The non-volatile semiconductor storage device according to claim 1 , further comprising:
a latch circuit latching an output signal of the sense amplifier; and
a selection switch receiving a latch signal latched by the latch circuit and a row-address signal, the selection switch inverting or not inverting the latch signal and outputting a resulting signal depending on whether the row-address signal indicates an even-numbered memory cell or an odd-numbered memory cell.
4. The non-volatile semiconductor storage device according to claim 1 , wherein
the write bit-line is formed as sandwiched between the corresponding read bit-line pair.
5. The non-volatile semiconductor storage device according to claim 1 , wherein
the word-line comprises a write word-line that is activated in data writing and a read word-line that is activated in data reading.
6. The non-volatile semiconductor storage device according to claim 1 , wherein
the memory cell comprises:
an antifuse device having a first end connected to a write power supply, the antifuse device storing data depending on whether a dielectric breakdown occurs due to a voltage applied across the first end and a second end of the antifuse device;
a write-selection transistor connected between the second end of the antifuse device and the write bit-line, the write-selection transistor being rendered conductive by a selection of the word-line; and
a read-selection transistor connected between the second end of the antifuse device and the read bit-line, the read-selection transistor being rendered conductive by the selection of the word-line.
7. The non-volatile semiconductor storage device according to claim 6 , wherein
the write-selection transistor has a larger size than the read-selection transistor.
8. The non-volatile semiconductor storage device according to claim 6 , wherein
the memory cell further comprises a barrier transistor, the barrier transistor being connected between the second end of the antifuse device and the read-selection transistor, the barrier transistor protecting the read-selection transistor.
9. The non-volatile semiconductor storage device according to claim 8 , wherein
the write-selection transistor has a larger size than the barrier transistor and the read-selection transistor.
10. The non-volatile semiconductor storage device according to claim 6 , wherein
the word-line comprises a write word-line that is selected in data writing and a read word-line that is selected in data reading,
the write-selection transistor is rendered conductive by a selection of the write word-line, and
the read-selection transistor is rendered conductive by a selection of the read word-line.
11. The non-volatile semiconductor storage device according to claim 1 , wherein
the write bit-line is a wiring of a single-line structure.
12. The non-volatile semiconductor storage device according to claim 11 , wherein
the write bit-line is formed as sandwiched between the corresponding read bit-line pair.
13. The non-volatile semiconductor storage device according to claim 11 , wherein
the write bit-line has a line width larger than that of one of the read bit-line pair.
14. The non-volatile semiconductor storage device according to claim 1 , wherein
the sense amplifier comprises:
a first-current bias circuit flowing a bias current through one of the read bit-line pair; and
a second-current bias circuit flowing a second bias current through the other one of the read bit-line pair.
15. The non-volatile semiconductor storage device according to claim 14 , further comprising:
a first bias-current control circuit activating the first-current bias circuit to supply said bias current through one of the read bit-line pair when an even-numbered memory cell is selected; and
a second bias-current control circuit activating the second-current bias circuit to supply said second bias current through the other one of the read bit-line pair when an odd-numbered memory cell is selected.