Method for fabricating semiconductor device
View Patent ↗A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.
1. A method for fabricating the semiconductor device, comprising:
providing a substrate with a trench therein, wherein a trench device is formed in the trench, and the trench device comprises two gate structures disposed on sidewalls of the trench, a doped region disposed in the substrate between the two gate structures and an inter-gate dielectric layer disposed on a surface of the two gate structures;
performing a first thermal treatment process in a nitrogen-containing ambient to remove a first native oxide layer formed on a surface of the doped region;
form a buffer layer in the trench; and
forming a conductive layer to fill the trench.
2. The method for fabricating the semiconductor device according to claim 1 , further comprising performing a second thermal treatment process in a nitrogen-containing ambient to remove a second native oxide layer formed on a surface of the buffer layer.
3. The method for fabricating the semiconductor device according to claim 2 , wherein the first and the second thermal treatment processes are a rapid thermal anneal process.
4. The method for fabricating the semiconductor device according to claim 2 , wherein a heating temperature of the first thermal treatment process and the second thermal treatment process is in a range of about 700-1000° C.
5. The method for fabricating semiconductor device according to claim 2 , wherein a heating time of the first thermal treatment process and the second thermal treatment process is in a range of 30-90 seconds.
6. The method for fabricating the semiconductor device according to claim 1 , wherein a material constituting the conductive layer comprises doped polysilicon.
7. The method for fabricating the semiconductor device according to claim 1 , wherein for the step of forming the conductive layer comprises performing chemical vapor deposition (CVD).
8. The method for fabricating the semiconductor device according to claim 1 , wherein a material constituting the buffer layer comprises an undoped poly silicon.
9. The method for fabricating the semiconductor device according to claim 1 , wherein each of the two gate structures comprises:
a gate disposed on sidewalls of the trench; and
a tunneling oxide layer disposed between the gate and the substrate.
10. The method for fabricating the semiconductor device according to claim 9 , wherein the gate is a floating gate, the doped region is a source region and the conductive layer is a source line.