On-chip variation, speed and power regulator
Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.
1. An integrated circuit chip, comprising:
a plurality of speed measurement elements formed in the chip and distributed about an operational area of the chip, each speed measurement element comprising a plurality of oscillators, each oscillator of the plurality of oscillators having an integrated circuit fabrication technology threshold different from integrated circuit fabrication technology thresholds of all other oscillators of the plurality of oscillators;
control circuitry formed in the chip and coupled to one or more of the speed measurement elements; and
a speed-measurement controller coupled to the speed measurement elements, the speed measurement controller selecting a technology threshold, wherein all oscillators having the selected technology threshold are enabled to operate.
2. The integrated circuit chip claimed in claim 1 , wherein the oscillators are ring oscillators.
3. The integrated circuit chip claimed in claim 1 , wherein the control circuitry comprises an interface element for communicating speed measurement data with an off-chip device.
4. The integrated circuit chip claimed in claim 3 , wherein the interface element comprises a programmable processing core.
5. The integrated circuit chip claimed in claim 3 , wherein the interface element comprises a Joint Test Action Group (JTAG) controller.
6. The integrated circuit chip claimed in claim 3 , wherein the speed measurement elements are daisy-chained to serially route output data from a speed measurement element through a chain of speed measurement elements to the interface element.
7. The integrated circuit chip claimed in claim 1 , wherein each speed measurement element comprises:
a first ring oscillator having a Standard Voltage Threshold;
a second ring oscillator having a Low Voltage Threshold; and
a third ring oscillator having a High Voltage Threshold.
8. The integrated circuit chip claimed in claim 1 , wherein the speed measurement controller comprises a sequencer, the sequencer sequentially selecting each integrated circuit fabrication technology threshold.
9. The integrated circuit chip claimed in claim 1 , wherein the speed measurement controller comprises a duration register, the duration register programmable with a duration value indicating how long the oscillators are enabled to operate.
10. A method for measuring on-chip variation (OCV) in operational speed of an integrated circuit chip having a plurality of speed measurement elements and an interface element, the speed measurement elements distributed about an operational area of the chip, each speed measurement element comprising a plurality of oscillators, each oscillator of the plurality of oscillators having an integrated circuit fabrication technology threshold different from integrated circuit fabrication technology thresholds of all other oscillators of the plurality of oscillators, the method comprising:
enabling operation of an oscillator having a first integrated circuit fabrication technology threshold in each of the speed measurement elements;
generating speed measurement data resulting from the operation of the oscillators having the first integrated circuit fabrication technology threshold;
enabling operation of an oscillator having a second integrated circuit fabrication technology threshold in each of the speed measurement elements; and
generating speed measurement data resulting from the operation of the oscillators having the second integrated circuit fabrication technology threshold by counting oscillation cycles.
11. The method claimed in claim 10 , further comprising:
enabling operation of an oscillator having a third integrated circuit fabrication technology threshold in each of the speed measurement elements;
generating speed measurement data resulting from the operation of the oscillators having the third integrated circuit fabrication technology threshold by counting oscillation cycles;
wherein the first integrated circuit fabrication technology threshold is a Standard Voltage Threshold;
wherein the second integrated circuit fabrication technology threshold is a Low Voltage Threshold; and
wherein the third integrated circuit fabrication technology threshold is a High Voltage Threshold.
12. The method claimed in claim 10 , further comprising programming a duration register of the chip with a duration value indicating how long the oscillators are enabled to operate before speed measurement data resulting from the operation is generated.
13. The method claimed in claim 12 , wherein:
the step of programming a duration register comprises operating a Joint Test Action Group (JTAG) controller on the chip; and
further comprising the step of transmitting the speed measurement data from the chip by operating the JTAG controller.
14. The method claimed in claim 10 , further comprising:
determining if the speed measurement data resulting from the operation of the oscillators having one of the first integrated circuit fabrication technology threshold and the second integrated circuit fabrication technology threshold indicates that a measured chip operational speed indicated by the speed measurement data is greater than a predetermined desired chip operational speed; and
decreasing chip core voltage of the integrated circuit chip if it is determined from the speed measurement data that measured chip operational speed is greater than the predetermined desired chip operational speed.
15. The method claimed in claim 14 , further comprising adjusting a chip operational parameter of the integrated circuit chip by adjusting a phase-locked loop input in response to the speed measurement data.