IP Library Granted Patent US 8,420,483
Granted Patent B2
US 8,420,483 · App. 11/971,169 · Granted Apr 16, 2013

Method of manufacture for a semiconductor device

Inventor: Mohamed N. Darwish (Campbell, CA)
Assignee: MaxPower Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,420,483
App. No.
11/971,169
Granted
Apr 16, 2013
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

Claims (24)

1. A process for making a transistor, comprising the actions, in any order except as specified below, of:

in a semiconductor material, forming a source region having a first conductivity type, a body region having a second conductivity type, and a drift region having said second conductivity type, wherein said drift region has a lower doping density than said body region;

forming at least one trench extending downward into said drift region of said semiconductor material; forming a dielectric layer on the inner surface of the trench; and thereafter

introducing ions in said dielectric layer to produce a substantially stable density of ions in proximity to sidewalls of said trench, to thereby produce an intentionally introduced fixed net electrostatic charge; and thereafter

substantially filling said trench with dielectric material, forming a recess in said trench, and forming a gate electrode in said recess which is capacitively coupled to said body region;

wherein said introducing step provides a density of said ions, in proximity to said drift region in said semiconductor material, which inverts the surface of said drift region of said semiconductor material;

wherein said introducing step also introduces ions into the bottom of said trench;

wherein said ions are cesium ions; and

wherein said semiconductor material is an epitaxial structure built on a substrate, and said trench extends into said epitaxial structure but not into said substrate.

2. The process of claim 1 , wherein said introducing step is performed by ion implantation.

3. The process of claim 1 , wherein said semiconductor material is silicon.

4. The process of claim 1 , wherein said gate electrode is a doped polycrystalline semiconductor material.

5. A process for making a transistor, comprising the actions, in any order except as specified below, of:

in a semiconductor material, forming a source region having a first conductivity type, a body region having a second conductivity type, and a drift region having said second conductivity type, wherein said drift region has a lower doping density than said body region;

forming at least one trench extending downward into said drift region of said semiconductor material; forming a dielectric layer on the inner surface of the trench; and thereafter

introducing ions in said dielectric layer to produce a stable density of net electrostatic charge in proximity to sidewalls of said trench, in sufficient concentration to invert at least part of said semiconductor material adjacent to said trench; and thereafter

filling said trench with dielectric material, forming a recess in said trench, and forming a gate electrode in said recess which is capacitively coupled to said body region;

wherein said introducing step also introduces ions into the bottom of said trench;

wherein said ions are cesium ions; and

wherein said semiconductor material is an epitaxial structure built on a substrate, and said trench extends into said epitaxial structure but not into said substrate.

6. The process of claim 5 , wherein said introducing step is performed by ion implantation.

7. The process of claim 5 , wherein said filling step fills said trench completely.

8. The process of claim 5 , wherein said filling step fills said trench completely without any voids.

9. The process of claim 5 , wherein said filling step fills said trench without any voids.

Assignments (2)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2008
From: DARWISH, MOHAMED N.
To: MAXPOWER SEMICONDUCTOR, INC.
Reel/Frame 020548/0728 →
Continuity (2)
Provisional Application 60879434 · Jan 9, 2007
Related Publication 20080166845A1 · Jul 10, 2008