Level shifter with balanced rise and fall times
View Patent ↗A level shifting circuit can include a shift stage that latches first and second internal nodes to opposite shifted logic potentials in response to different transitions at an input signal node. The input signal node can vary between non-shifted logic potentials. An output stage can enable a first controllable impedance path coupled between an output node and a first shifted power supply node in response to a first type transition at the first internal node, and can enable a second controllable impedance path coupled between the output node and a second shifted power supply node in response to the first type transition at the second internal node.
1. A level shifting circuit, comprising:
a shift stage that latches first and second internal nodes to opposite shifted logic potentials in response to different transitions at an input signal node, the input signal node varying between non-shifted logic potentials;
an output stage that enables a first controllable impedance path coupled between an output node and a first shifted power supply node in response to a first type transition at the first internal node, and enables a second controllable impedance path coupled between the output node and a second shifted power supply node in response to the first type transition at the second internal node; and
a keeper circuit that maintains the output node at a predetermined shifted logic potential and includes
a first break switch coupled to the output node that is disabled in response to a potential at one of the internal nodes, and
a first feedback switch coupled between the first break switch and one of the shifted power supply nodes that is enabled in response to a potential at the output node.
2. The level shifting circuit of claim 1 , wherein the shift stage comprises:
a first transistor having a controllable current path coupled between the first internal node and the first shifted power supply node and a control terminal coupled to the second internal node, and
a second transistor having a controllable current path coupled between the second internal node and the first shifted power supply node and a control terminal coupled to the first internal node.
3. The level shifting circuit of claim 1 , wherein the shift stage comprises:
a first input transistor having a controllable current path coupled between the first internal node and the second shifted power supply node and a control terminal coupled to the input signal node, and
a second input transistor having a controllable current path coupled between the second internal node and the second shifted power supply node and a control terminal coupled to the input signal node.
4. The level shifting circuit of claim 1 , further comprising:
an input stage comprising
a non-inverting signal path that provides a non-inverted version of an input signal to the shift stage, and
an inverting signal path that provides an inverted version of the input signal to the shift stage.
5. The level shifting circuit of claim 1 , wherein the keeper circuit includes:
the first break switch being disabled in response to a potential at the first internal node,
the first feedback switch being coupled between the first break switch and the second shifted power supply node,
a second break switch coupled to the output node that is disabled in response to a potential at the second internal node, and
a second feedback switch coupled between the second break switch and the first shifted power supply node, the second feedback switch being enabled in response to a potential at the output node.
6. A method of signal balancing for a level shifting circuit, comprising:
in response to a first type input transition in an input signal that varies between non-shifted voltage levels, forcing a first type transition at a first internal node by causing a bistable circuit to switch from a first state to a second state after a first delay, and driving an output node to a high shifted voltage in response to the first type transition at the first internal node;
in response to a second type input transition in the input signal, forcing the first type transition at a second internal node by causing the bistable circuit to switch from the second state to the first state after essentially the first delay, and driving the output node to a low shifted voltage in response to the first type transition at the second internal node;
after driving the output node to the high shifted voltage, keeping the output node at the high shifted voltage with a first keeper device; and
isolating the first keeper device from the output node in the event the second internal node makes the first type transition.
7. The method of claim 6 , wherein:
the step of causing the bistable circuit to switch from the first state to the second state includes driving the first internal node to a first shifted voltage level from a second shifted voltage level to thereby latch the second internal node at the second shifted voltage level, and
the step of causing the bistable circuit to switch from the second state to the first state includes driving the second internal node to the first shifted voltage level from the second shifted voltage level to thereby latch the first internal node at the second shifted voltage level.
8. The method of claim 6 , wherein:
the high and low shifted voltage levels include a first voltage and a shifted voltage and the non-shifted voltage levels include the first voltage and a non-shifted voltage; and
the first type transition includes a transition from the first voltage to the shifted voltage.
9. The method of claim 6 , further including:
inverting the input signal to create an inverted input signal; and
latching the first and second internal nodes at opposite shifted voltage levels includes
in response to the input signal transitioning to a first non-shifted voltage level, driving a first internal node to a first shifted voltage level from a second shifted voltage level to thereby latch the second internal node at the second shifted voltage level, and
in response to the inverted input signal transitioning to the first non-shifted voltage level, driving the second internal node to the first shifted voltage level from the second shifted voltage level to thereby latch the first internal node at the second shifted voltage level.
10. The method of claim 6 , further including:
after driving the output node to the low shifted voltage, keeping the output node at the low shifted voltage level with a second keeper device; and
isolating the second keeper device from the output node in the event the first internal node makes the first type transition.
11. The method of claim 6 , further including:
generating the input signal with a timing circuit formed on a first portion of an integrated circuit that receives the non-shifted voltage levels as power supply voltage levels; and
enabling a data transmission path in response to the potential at the output node, the data transmission path being formed on a second portion of the integrated circuit that receives the shifted voltage levels as power supply voltage levels.
12. A level shifting circuit, comprising:
a means for shifting that latches first and second internal nodes to opposite shifted logic potentials in response to different transitions in a first input signal that varies within a low voltage range;
output means for coupling an output node to a first shifted power supply node in response to a first type transition at the first internal node after a first delay, and for coupling the output node to a second shifted power supply node in response to the first type transition at the second internal node after a second delay; wherein the low voltage range is less than a difference between the opposite shifted logic potentials and the first delay is essentially the same as the second delay; and
keeper means for
maintaining the output node at a second shifted logic level after the second internal node makes the first type transition with a first feedback device coupled to the output node, and
isolating the first feedback device from the output node in the event the first internal node makes the first type transition.
13. The level shifting circuit of claim 12 , wherein:
the keeper means further includes
maintaining the output node at a first shifted logic level after the first internal node makes the first type transition with a first feedback device coupled to the output node.
14. An integrated circuit device, comprising:
a shift stage that, in response to a first type transition of an input signal, drives a first internal node to a first shifted voltage, and after a first delay, drives a second internal node to a second shifted voltage, and in response to a second type transition of the input signal, drives the second internal node to the first shifted voltage, and after a second delay, drives the first internal node to the second shifted voltage;
an output stage that enables a first controllable impedance path coupled between an output node and a first shifted voltage in response to the potential at the first internal node through a first output circuit signal path, and enables a second controllable impedance path coupled between the output node and a second shifted voltage in response to the potential at the second internal node through a second output circuit signal path; and
a data path circuit that enables or prevents a data signal to propagate through a signal path in response to the potential at the output node.
15. The integrated circuit of claim 14 , further including:
an input section having
an input coupled to receive the input signal,
a non-inverting signal path that provides a non-inverted version of the input signal to the shift stage after a first input delay, and
an inverting signal path that provides an inverted version of the input signal to the shift stage after a second input delay, wherein the second input delay is essentially the same as the first input delay.
16. The integrated circuit of claim 14 , wherein the output stage further includes:
a first keeper circuit that maintains the output node at the first shifted voltage via a feedback path coupled to the output node.
17. The integrated circuit of claim 14 , wherein:
the difference between levels of the input signal is less than the difference between the first and second shifted voltages, the first delay is essentially the same as the second delay, and the first and second output circuit signal paths introduce essentially the same signal delay.
18. The integrated circuit of claim 14 , further including:
a timing circuit that generates a periodic signal as the first input signal;
a content addressable memory (CAM) cell section; and
the data path circuit is selected from the group consisting of: data input circuits that couple data from input terminals of the integrated circuit to the CAM cell section and data output circuits that couple data from the CAM cell section to output terminals of the integrated circuit.