Multiphase clock generation circuit
View Patent ↗Provided is a multiphase clock generation circuit ( 1 ) including: a phase-locked loop circuit ( 10 ) for generating multiphase clock signals based on a reference clock signal; a frequency profile holding circuit ( 20 ) for holding a frequency profile of each of the multiphase clock signals, starting output of the frequency profile in response to a start signal, and for updating the frequency profile with a predetermined cycle based on the reference clock signal; and a clock selection circuit ( 30 ) for selecting a clock signal with an arbitrary phase from among the multiphase clock signals based on the frequency profile, and for feeding back the selected clock signal to the phase-locked loop circuit ( 10 ).
1. A multiphase clock generation circuit, comprising:
a phase-locked loop circuit for generating multiphase clock signals based on a reference clock signal;
a frequency profile holding circuit for holding a frequency profile of each of the multiphase clock signals, starting output of the frequency profile in response to a start signal, and for updating the frequency profile with a predetermined cycle based on the reference clock signal; and
a clock selection circuit for selecting a clock signal with an arbitrary phase from among the multiphase clock signals based on the frequency profile, and for feeding back the selected clock signal to the phase-locked loop circuit,
wherein the frequency profile holding circuit comprises:
a first counter for counting a number of clocks of the reference clock signal; and
a memory for holding the frequency profile; and
the frequency profile holding circuit updates the frequency profile to be output from the memory according to the number of clocks.
2. The multiphase clock generation circuit according to claim 1 , wherein the first counter starts counting of the number of clocks of the reference clock signal in response to the start signal.
3. The multiphase clock generation circuit according to claim 1 , wherein:
the frequency profile contains a fine adjustment period set value for dividing the predetermined cycle at an arbitrary ratio; and
the clock selection circuit finely adjusts a phase change width of the clock signal to be selected based on the fine adjustment period set value.
4. The multiphase clock generation circuit according to claim 3 , wherein the clock selection circuit changes the phase change width of the clock signal to be selected based on a change width set value contained in the frequency profile, and finely adjusts a phase change width designated by the change width set value, based on the fine adjustment period set value.
5. The multiphase clock generation circuit according to claim 1 , wherein:
the frequency profile holding circuit comprises a first counter for counting the number of clocks of the reference clock signal;
the clock selection circuit comprises:
a second counter having a maximum count value which is the same as that of the first counter, for counting the number of clocks of the reference clock signal; and
a comparator for comparing a count value output from the second counter and a fine adjustment period set value for dividing the predetermined cycle at an arbitrary ratio, the fine adjustment set value being output from the frequency profile holding circuit;
the comparator outputs a comparison signal according to the fine adjustment period set value; and
the clock selection circuit finely adjusts a change width set value contained in the frequency profile in response to the comparison signal, and selects a clock signal with a phase to be fed back from among the multiphase clock signals based on the finely adjusted change width set value.
6. The multiphase clock generation circuit according to claim 1 , wherein the multiphase clock generation circuit comprises a clock generation circuit for generating a clock signal for adjusting a pulse width of a pulse width modulation circuit for outputting a pulse signal for modulating a laser output.
7. A multiphase clock generator, comprising:
a phase-locked loop circuit generating multiphase clock signals in response to a reference clock signal and a feed-back clock signal;
a frequency profile holding circuit for holding frequency profile information; and
a clock selection circuit selecting one of the multiphase clock signals in response to frequency profile information and providing selected clock signal to the phase-locked loop circuit as the feed-back clock signal, the frequency profile holding circuit further updating the frequency profile information to produce updated frequency profile information,
wherein the frequency profile holding circuit comprises:
a first counter for counting a number of clocks of the reference clock signal; and
a memory for holding the frequency profile; and
the frequency profile holding circuit updates the frequency profile to be output from the memory according to the number of clocks.
8. The generator according to claim 7 , wherein the updated frequency profile information is further supplied to the clock selection circuit to select another one of the multiphase clock signals.