Method for manufacturing a resistor random access memory with a self-aligned air gap insulator
A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.
1. A memory device comprising:
a bottom electrode;
a top electrode;
a multi-layer stack comprising a plurality of layers, the multi-layer stack contacting the top and bottom electrodes to define an inter-electrode current path through each of said layers between the top and bottom electrodes, the multi-layer stack including a first heater layer and a second heater layer and a memory element comprising a programmable resistive memory material, the memory element being sandwiched by the first heater layer and the second heater layer, the multi-layer stack having a sidewall surface defining a width of the first heater layer and of the second heater layer and of the memory element transverse to the inter-electrode current path which is less than a width of a top surface of the bottom electrode in contact with the multi-layer stack; and
an air gap adjacent to the sidewall surface of the memory element, the first heater layer, and the second heater layer and self-aligned to the memory element.
2. The device of claim 1 , wherein the memory element has a width less than a minimum feature size for a lithographic process used to form the memory device.
3. The device of claim 1 , wherein the air gap completely surrounds the memory element.
4. The device of claim 1 , wherein:
the first heater layer is on the bottom electrode, the memory element is on the first heater layer; and
the second heater layer is on the memory element.
5. The device of claim 4 , wherein the first and second heater layers comprise a material from the group consisting of TiN, TaN, TiAlN, TaAlN, TiW, TiSiN, or TaSiN.
6. The device of claim 1 , wherein the programmable resistive memory material comprises a combination of two or more materials from the group consisting of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, or Au.
7. The device of claim 1 , wherein the memory element has a width between about 50 nm and about 80 nm.
8. The device of claim 4 , wherein the top electrode has a bottom surface in contact with a top surface of the second heater layer, the bottom surface of the top electrode having a width the same as that of the top surface of the second heater layer.
9. The device of claim 8 , wherein the top electrode comprises a portion of a bit line.
10. The device of claim 4 , wherein the multi-layer stack has a width less than a width of a top surface of the bottom electrode in contact with the first heater layer.
11. The device of claim 4 , wherein the first and second heater layers have sides aligned with sides of the memory element, so that the first and second heater layers and the memory element have substantially the same width.
12. A memory device comprising:
a bottom electrode;
a top electrode;
a multi-layer stack comprising a plurality of layers, the multi-layer stack contacting the top and bottom electrodes to define an inter-electrode current path through each of said layers between the top and bottom electrodes, the multi-layer stack including a first heater layer and a second heater layer and a memory element comprising a programmable resistive memory material, the memory element being sandwiched by the first heater layer and the second heater layer, the multi-layer stack having a sidewall surface defining a width of the first heater layer and of the second heater layer and of the memory element transverse to the inter-electrode current path which is less than a width of a top surface of the bottom electrode in contact with the multi-layer stack; and
an air gap adjacent to the sidewall surface of the memory element, the first heater layer, and the second heater layer and self-aligned to the memory element, wherein the sidewall of the memory element is fully surrounded by the air gap.
13. The device of claim 12 , wherein the memory element has a width less than a minimum feature size for a lithographic process used to form the memory device.
14. The device of claim 12 , wherein:
the first heater layer is on the bottom electrode, the memory element is on the first heater layer; and
the second heater layer is on the memory element.
15. The device of claim 14 , wherein the first and second heater layers comprise a material from the group consisting of TiN, TaN, TiAlN, TaAlN, TiW, TiSiN, or TaSiN.
16. The device of claim 12 , wherein the programmable resistive memory material comprises a combination of two or more materials from the group consisting of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, or Au.
17. The device of claim 12 , wherein the memory element has a width between about 50 nm and about 80 nm.
18. The device of claim 14 , wherein the top electrode has a bottom surface in contact with a top surface of the second heater layer, the bottom surface of the top electrode having a width the same as that of the top surface of the second heater layer.
19. The device of claim 18 , wherein the top electrode comprises a portion of a bit line.
20. The device of claim 14 , wherein the multi-layer stack has a width less than a width of a top surface of the bottom electrode in contact with the first heater layer.
21. The device of claim 14 , wherein the first and second heater layers have sides aligned with sides of the memory element, so that the first and second heater layers and the memory element have substantially the same width.