PC-based computing system employing parallelized GPU-driven pipeline cores integrated with a routing unit and control unit on a silicon chip of monolithic construction
A PC-based computing system employing parallelized GPU-driven pipeline cores integrated with a routing unit and control unit on a silicon chip of monolithic construction. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers, and graphics libraries. The system also includes a CPU/memory interface module, a CPU bus, a silicon chip of monolithic construction interfaced with the CPU/memory interface module. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from software multi-pipe drivers, and controls components within said silicon chip, including said routing unit. In a preferred embodiment, the silicon chip also has a display interface, providing a complete multi-processor system-on-a-chip (MP-SOC) architecture.
1 . A PC-based computing system comprising:
system memory for storing software graphics applications, software drivers and graphics libraries;
an operating system (OS), stored in said system memory;
one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user of said PC-based computing system;
one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;
a central processing unit (CPU), for executing said OS, said graphics applications, said drivers and said graphics libraries;
a CPU bus;
a CPU/memory interface module for interfacing with said CPU by way of said CPU bus;
a display surface for displaying said images by graphically displaying frames of pixel data;
software multi-pipe drivers, stored in said system memory, and including a GPU driver module; and
a silicon chip on its monolithic construction having integrated thereon,
(i) a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to a parallelization mode of operation so that said GPU-driven pipeline cores process data in a parallel manner,
(ii) a routing unit and interfacing with said CPU/memory interface module, and
(iii) a control unit for accepting commands from said software multi-pipe drivers, and controlling components within said silicon chip, including said routing unit;
wherein said GPU driver module allows said GPU-driven pipeline cores to interact with said OS and said graphic libraries;
wherein said routing unit (i) routes the stream of geometrical data and graphic commands from said graphics application to one or more of said GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface;
wherein said CPU/memory interface module provides an interface between said software multi-pipe drivers and said silicon chip;
wherein said software multi-pipe drivers perform the following functions:
(i) controlling the operation of said silicon chip,
(ii) interacting with said OS and said graphic libraries, and
(iii) forwarding said stream of geometrical data and graphic commands, or a portion thereof, over said CPU bus to each said GPU-driven pipeline core; and
wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed:
(i) said silicon chip uses said routing unit to distribute said stream of geometrical data and graphic commands, or a portion thereof, to said GPU-driven pipeline cores,
(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and
(iii) said silicon chip uses said routing unit to transfer said pixel data output from one or more of said GPU-driven pipeline cores and compose a frame of pixel data, representative of the image of said 3D object, for display on said display surface.
2 . The PC-based computing system of claim 1 , wherein said silicon chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.
3 . The PC-based computing system of claim 1 , wherein said CPU/memory interface module is an I/O chip or chipset.
4 . The PC-based computing system of claim 1 , wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.
5 . The PC-based computing system of claim 1 , wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.
6 . The PC-based computing system of claim 1 , wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.
7 . The PC-based computing system of claim 1 , wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.
8 . The PC-based computing system of claim 1 , wherein said software multi-pipe drivers coordinate the operation of said GPU-driven pipeline cores so generate a continuous sequence of frames of pixel data for displaying a sequence of images of said 3D object on said display surface.
9 . The PC-based computing system of claim 1 , wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.
10 . The PC-based computing system of claim 1 , wherein said parallelization mode of operation is a time division mode of parallel operation.
11 . The PC-based computing system of claim 1 , wherein said parallelization mode of operation is an image division mode of parallel operation.
12 . The PC-based computing system of claim 1 , wherein said parallelization mode of operation is an object division mode of parallel operation.
13 . The PC-based computing system of claim 13 , wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.
14 . The PC-based computing system of claim 1 , wherein the number of said GPU-driven pipeline cores has no architectural limit.
15 . The PC-based computing system of claim 1 , wherein silicon chip further includes a display interface for interfacing with a display surface capable of displaying images consisting of pixel data composited by said GPU-driven pipeline cores.
16 . The PC-based computing system of claim 16 , wherein said silicon chip is realized as a multi-processor system-on-a-chip (MP-SOC) architecture.
17 . The PC-based computing system of claim 18 , which further comprises a graphics card, and wherein said silicon chip is mounted on said graphics card.