Silicon chip of monolithic construction for integration in a PC-based computing system and having multiple GPU-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics application

1 . A silicon chip of monolithic construction and software multi-pipe drivers for integration in a PC-based computing system and parallelizing multiple GPU-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics application, wherein said PC-based computing system includes (i) system memory for storing software graphics applications, software drivers and graphics libraries, (ii) an operating system (OS), stored in said system memory, (iii) one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting the representation of one or more 3D objects in a scene having 3D geometrical characteristics and the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user thereof, (iv) one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands, (v) a central processing unit (CPU) for executing said OS, said graphics applications, said drivers and said graphics libraries, (vi) a CPU bus, (vii) an CPU/memory interface module, and (viii) a display surface for displaying said images by graphically displaying frames of pixel data; wherein said silicon chip comprises:

a routing unit;

a control unit; and

a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to one or more parallelization modes of operation, determined during the generation of each said frame of pixel data, so that said GPU-driven pipeline cores process data in a parallel manner;

wherein said software multi-pipe drivers are stored in said system memory;

wherein said one or more parallelization modes of operation include a time division mode, an image division mode, and an object division;

wherein said routing unit (i) routes the stream of geometrical data and graphic commands from said graphics application to one or more of said GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface;

wherein said control unit accepts commands from said software multi-pipe drivers, and controls components within said silicon chip, including said routing unit;

wherein said software multi-pipe drivers perform the following functions:

(i) controlling the operation of said silicon chip,

(ii) interacting with said OS and said graphic libraries,

(ii) dynamically determining and controlling said parallelization mode during the generation of each said frame of pixel data during the running of said graphics application, and

(iii) forwarding said stream of geometrical data and graphic commands, or a portion thereof, over said CPU bus to each said GPU-driven pipeline core; and

wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed:

(i) said silicon chip uses said routing unit to distribute said stream of geometrical data and graphic commands, or a portion thereof, to said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said silicon chip uses said routing unit to route said pixel data output from one or more of said GPU-driven pipeline cores and compose a frame of pixel data, representative of the image of said 3D object, for display on said display surface.

2 . The silicon chip of claim 1 , which further comprises a profiling unit for profiling the performance of said GPU-driven pipeline cores and feeding back said performance data to said software multi-pipe drivers.

3 . The silicon chip of claim 1 , which further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.

4 . The silicon chip of claim 1 , wherein said CPU/memory interface module is an I/O chip or chipset.

5 . The silicon chip of claim 1 , wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.

6 . The silicon chip of claim 1 , wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

7 . The silicon chip of claim 1 , wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

8 . The silicon chip of claim 1 , wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

9 . The silicon chip of claim 1 , wherein said software multi-pipe drivers coordinate the operation of said GPU-driven pipeline cores so generate a continuous sequence of frames of pixel data for displaying a sequence of images of said 3D object on said display surface.

10 . The silicon chip of claim 1 , wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.

11 . The silicon chip of claim 1 , wherein when said parallelization mode of operation is said time division mode, each said GPU renders a different frame of pixel data for display on said display surface at a different moment of time.

12 . The silicon chip of claim 1 , wherein when said parallelization mode of operation is said image division mode, each GPU renders a subset of the pixels used to compose each frame of pixel data to be displayed on said display surface.

13 . The silicon chip of claim 1 , wherein when said parallelization mode of operation is said object division mode, the 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of geometrical data and graphic commands which are distributed to said GPU-driven pipeline cores for rendering the frames of pixel data compositing the images to be displayed on said display surface.

14 . The silicon chip of claim 13 , wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

15 . The silicon chip of claim 1 , wherein said software multi-pipe drivers further comprise one or more of the following software modules installed in said system memory:

(1) a GPU drivers module for allowing said GPU-driven pipeline cores to interact with said OS and said graphic libraries;

(2) a distributed graphic functions control module for performing functions associated with carrying on said parallelization modes according to a parallelization policy management;

(3) a state monitoring driver module for continuously analyzing substantially all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphic pipeline cores;

(4) an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said PC-based computing system, identifying problem areas likely to cause data bottlenecks;

(5) parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by said control unit.

16 . The silicon chip of claim 15 , wherein said application profiling and analysis driver modules uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, and (ii) registers of said control unit, and graphic API commands.

17 . The silicon chip of claim 1 , wherein when said parallelization mode of operation is said object division mode of parallel operation, wherein the 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of geometrical data and graphic commands which are distributed to said GPU-driven pipeline cores for rendering the frames of pixel data compositing the images to be displayed on said display surface.

18 . The silicon chip of claim 1 , wherein said dynamically determining and controlling said parallelization mode during any particular frame of pixel data generation and display is based on factors including the time required to render previous frames of pixel data and bottlenecks exhibited in vertex processing and pixel processing during the rendering of said previous frames of pixel data.

19 . The silicon chip of claim 1 , wherein said parallelization mode operation is based on any combination of said object division mode, said image division mode and said time division mode.

20 . The silicon chip claim 1 , wherein during said dynamically determining and controlling said parallelization mode, said software multi-pipe drivers analyze collected parameters including data selected from the group consisting of: memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among graphic pipelines, volumes of transferred data, textures count, and depth complexity.

21 . The silicon chip of claim 1 , wherein the number of said GPU-driven pipeline cores has no architectural limit.

22 . The silicon chip of claim 1 , wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

23 . The silicon chip of claim 1 , wherein at least one said GPU-driven pipeline core is realized on said silicon chip, along with said routing unit and said control unit.

24 . The silicon chip of claim 1 , in combination with a graphics card on which said silicon chip is mounted.

25 . The silicon chip of claim 1 , having a multi-processor system-on-a-chip (MP-SOC) architecture.