IP Library Granted Patent US 8,106,442
Granted Patent B2
US 8,106,442 · App. 11/979,183 · Granted Jan 31, 2012

NROM fabrication method

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Quick Facts
Patent No.
US 8,106,442
App. No.
11/979,183
Granted
Jan 31, 2012
Kind
B2
Abstract

A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A further method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.

Claims (20)

1. A non-volatile memory cell comprising: a charge trapping layer comprised of a silicon nitride based dielectric, wherein said silicon nitride based dielectric includes a non-native and non-silicone based impurity and is at least partially located substantially above a channel of the cell.

2. The cell according to claim 1 , wherein said non-native impurity is oxygen.

3. The cell according to claim 2 , wherein said oxygen concentration is between approximately 10% and 80%.

4. The cell according to claim 1 , wherein said charge trapping layer is located substantially above an oxide layer having a thickness greater than 30 angstroms.

5. The cell according to claim 1 , wherein said charge trapping layer has a thickness of between approximately 20 and 150 angstroms.

6. The cell according to claim 1 , wherein said charge trapping layer has a thickness of between approximately 10 and 50 angstroms.

7. A non-volatile memory cell comprising: a charge trapping layer comprised of an impure silicon based dielectric located at least partially substantially above a channel of the cell, wherein said impurity is non-silicone based.

8. The cell according to claim 7 , wherein said impure silicon based dielectric is selected from the group consisting of silicon dioxide and silicon nitride.

9. The cell according to claim 7 , wherein the charge trapping layer is oxinitride.

10. The cell according to claim 7 , wherein the charge trapping layer has a thickness between approximately 20 and 50 angstroms.

11. The cell according to claim 7 , wherein the charge trapping layer has a thickness between approximately 10 and 150 angstroms.

12. The cell according to claim 7 , wherein at least a portion of the charge trapping layer is located substantially above an oxide layer having a thickness greater than approximately 30 angstroms.

13. A non-volatile memory cell comprising: a charge trapping layer comprised of an impure silicone based dielectric located at least partially substantially below a gate of the cell, wherein said impurity is non-silicone based.

14. The cell according to claim 13 , wherein said impure silicon based dielectric is selected from the group consisting of silicon dioxide and silicon nitride.

15. The cell according to claim 13 , wherein the charge trapping layer has a thickness between approximately 20 and 150 angstroms.

16. The cell according to claim 13 , wherein the charge trapping layer has a thickness between approximately 10 and 50 angstroms.

17. A non-volatile memory cell comprising: a charge trapping layer comprised of a silicon nitride based dielectric, wherein said silicon nitride based dielectric includes a non-native and non-silicone based impurity and is located substantially above a channel of the cell, wherein said impurity includes oxygen atoms.

18. The cell according to claim 17 , wherein said oxygen atoms are adapted to inhibit charge migration.

19. The cell according to claim 17 , wherein said dielectric has a thickness of between approximately 20 and 150 angstroms.

20. The cell according to claim 17 , wherein said dielectric has a thickness of between approximately 10 and 50 angstroms.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
CHANGE OF NAME Recorded Jun 12, 2012
From: SAIFUN SEMICONDUCTORS LTD.
To: SPANSION ISRAEL LTD
Reel/Frame 028356/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2008
From: EITAN, BOAZ
To: SAIFUN SEMICONDUCTORS LTD.
Reel/Frame 020374/0966 →