IP Library › Patent Application 11979799
Patent Application
App. No. 11/979,799

Gradation potential generation circuit, data driver of display device and the display device

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Quick Facts
Patent No.
US None
App. No.
11/979,799
Abstract

A gradation potential generation circuit includes a first ladder resistance circuit supplied with a first and a second reference voltages to both ends to generate j number of gradation potentials (j is an integer of 2 or more) and output the generated j number of gradation potentials to j number of first nodes, where the j number of gradation potentials being generated by dividing the first and the second reference voltages, a second ladder resistance circuit to generate k number of gradation potentials out of the j number of gradation potentials (where j>k) generated by the first ladder resistance circuit and k number of switches to supply the k number of gradation potentials generated by the second ladder resistance circuit to k number of first nodes out of the j number of first nodes according to a first control signal.

Claims (27)

1 . A gradation potential generation circuit comprising:

a first ladder resistance circuit supplied with a first and a second reference voltages to both ends to generate j number of gradation potentials (j is an integer of 2 or more) and output the generated j number of gradation potentials to j number of first nodes, the j number of gradation potentials being generated by dividing the first and the second reference voltages;

a second ladder resistance circuit to generate k number of gradation potentials out of the j number of gradation potentials (where j>k) generated by the first ladder resistance circuit; and

k number of switches to supply the k number of gradation potentials generated by the second ladder resistance circuit to k number of first nodes out of the j number of first nodes according to a first control signal.

2 . The gradation potential generation circuit according to claim 1 , wherein the j number of gradation potentials include at least one of the first and the second reference voltages.

3 . The gradation potential generation circuit according to claim 1 , wherein the second ladder resistance circuit has a resistance value lower than the first ladder resistance circuit.

4 . The gradation potential generation circuit according to claim 2 , wherein the second ladder resistance circuit has a resistance value lower than the first ladder resistance circuit.

5 . The gradation potential generation circuit according to claim 1 , wherein the k number of gradation potentials generated by the second ladder resistance circuit have a large potential difference between adjacent gradation potentials near the first and the second reference voltages and a small potential difference between adjacent gradation potentials near the intermediate voltage of the first and the second reference voltages.

6 . The gradation potential generation circuit according to claim 2 , wherein the k number of gradation potentials generated by the second ladder resistance circuit have a large potential difference between adjacent gradation potentials near the first and the second reference voltages and a small potential difference between adjacent gradation potentials near the intermediate voltage of the first and the second reference voltages.

7 . The gradation potential generation circuit according to claim 3 , wherein the k number of gradation potentials generated by the second ladder resistance circuit have a large potential difference between adjacent gradation potentials near the first and the second reference voltages and a small potential difference between adjacent gradation potentials near the intermediate voltage of the first and the second reference voltages.

8 . A data driver of a display device comprising:

the gradation potential generation circuit according to claim 1 ;

a decoding circuit input with j number of gradation potentials generated by the gradation potential generation circuit and digital gradation data corresponding to an image data signal to select a gradation potential corresponding to the digital gradation data;

an amplifier circuit to amplify and output a gradation potential output from the decoding circuit; and

an output switch connected between an output end of the amplifier circuit and a data line to supply an output signal of the amplifier circuit to the data line according to a second control signal.

9 . A data driver of a display device according to claim 8 , wherein the j number of gradation potentials include at least one of the first and the second reference voltages.

10 . A data driver of a display device according to claim 8 , wherein the second ladder resistance circuit has a resistance value lower than the first ladder resistance circuit.

11 . A data driver of a display device according to claim 8 , wherein the k number of gradation potentials generated by the second ladder resistance circuit have a large potential difference between adjacent gradation potentials near the first and the second reference voltages and a small potential difference between adjacent gradation potentials near the intermediate voltage of the first and the second reference voltages.

12 . The data driver of the display device according to claim 8 , wherein the output switch is turned off in a first period within one selection period when a gradation potential is selected by the decoding circuit and turned on in a second period within the one selection period, and

the k number of switches between the first and the second ladder resistance circuits of the gradation potential generation circuit are turned on in a predetermined period within the first period and turned off in the second period.

13 . The data driver of the display device according to claim 9 , wherein the output switch is turned off in a first period within one selection period when a gradation potential is selected by the decoding circuit and turned on in a second period within the one selection period, and

the k number of switches between the first and the second ladder resistance circuits of the gradation potential generation circuit are turned on in a predetermined period within the first period and turned off in the second period.

14 . The data driver of the display device according to claim 10 , wherein the output switch is turned off in a first period within one selection period when a gradation potential is selected by the decoding circuit and turned on in a second period within the one selection period, and

the k number of switches between the first and the second ladder resistance circuits of the gradation potential generation circuit are turned on in a predetermined period within the first period and turned off in the second period.

15 . The data driver of the display device according to claim 11 , wherein the output switch is turned off in a first period within one selection period when a gradation potential is selected by the decoding circuit and turned on in a second period within the one selection period, and

the k number of switches between the first and the second ladder resistance circuits of the gradation potential generation circuit are turned on in a predetermined period within the first period and turned off in the second period.

16 . A display device comprising the data driver according to claim 8 .

Assignments (2)
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2007
From: UMEDA, KENGO; TSUCHI, HIROSHI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020149/0764 →