IP Library › Granted Patent US 7,629,632
Granted Patent B2
US 7,629,632 · App. 11/980,567 · Granted Dec 8, 2009

Insulated-gate field effect transistor

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,629,632
App. No.
11/980,567
Granted
Dec 8, 2009
Kind
B2
Abstract

In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one on another on the AlGaN barrier layer 104. Since the p-type polycrystalline SiC layer 109 is relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.

Claims (17)

1. An insulated-gate field effect transistor comprising:

a semiconductor channel layer in which a first conductive-type channel is formed;

a source electrode formed on the semiconductor channel layer;

a drain electrode formed on the semiconductor channel layer;

a gate insulator formed on the semiconductor channel layer;

a second conductive-type semiconductor film formed on the gate insulator; and

a gate electrode formed on the second conductive-type semiconductor film and made of a metallic ohmic electrode, wherein

the gate electrode made of a metallic ohmic electrode serves as a first gate electrode, and

the insulated-gate field effect transistor further comprises a second gate electrode which is formed of a Schottky electrode formed on the semiconductor channel layer and between the first gate electrode and the drain electrode and which is electrically connected to the source electrode.

2. The insulated-gate field effect transistor as claimed in claim 1 , wherein

the second conductive-type semiconductor film is fabricated from a polycrystalline semiconductor or amorphous semiconductor.

3. The insulated-gate field effect transistor as claimed in claim 1 , wherein

the semiconductor channel layer is fabricated from a group III-V compound semiconductor.

4. The insulated-gate field effect transistor as claimed in claim 3 , wherein

the gate insulator is made of Ta 2 O 5 .

5. The insulated-gate field effect transistor as claimed in claim 3 , wherein

the gate insulator is made of silicon nitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2019
From: SHARP KABUSHIKI KAISHA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 049403/0835 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2008
From: TWYNAM, JOHN
To: SHARP KABUSHIKI KAISHA
Reel/Frame 020706/0652 →
Priority Claims (1)
JP 2006-309107 · Nov 15, 2006 · national
Continuity (1)
Related Publication 20080210988A1 · Sep 4, 2008