Method for a general near optimal turbo code trellis termination
A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.
1. A method for terminating two constituent encoders of a turbo encoder employing a turbo code, the method comprising:
encoding information bits input to a first one of the two constituent encoders and encoding the information bits input to a second one of the two constituent encoders, wherein the information bits input into the second of the two constituent encoders are interleaved;
generating tail output bits after encoding the information bits; and
outputting tail output bits from each of the two constituent encoders during trellis termination of the two constituent encoders,
wherein a first set of the tail output bits is generated by the first of the two constituent encoders while the second of the two constituent encoders is disabled and a second set of the tail output bits is generated by the second of the two constituent encoders while the first of the two constituent encoders is disabled.
2. The method of claim 1 , wherein outputting the tail output bits further comprises:
outputting at least one tail output bit from the first of the two constituent encoders more than once; and
outputting at least one tail output bit from the second of the two constituent encoders more than once.
3. The method of claim 1 , wherein the turbo encoder is employed as a coding rate (R) turbo encoder, wherein R is ½, ⅓ or ¼.
4. The method of claim 3 , further comprising inputting the tail input bits consecutively at each of the two constituent encoders such that tail input bits are input to the first of the two constituent encoders in different clock cycles than tail input bits input to the second of the two constituent encoders.
5. The method of claim 3 , further comprising:
puncturing one or more tail output bits output from each of the two constituent encoders.
6. The method of claim 3 , wherein R is ½ and outputting the tail output bits comprises:
outputting tail output bits from a first output branch, X(t), and a second output branch, Y0(t), of the first constituent encoder; and
outputting tail output bits from a third output branch, X′(t), and a fourth output branch, Y0′(t), of the second constituent encoder.
7. The method of claim 6 , wherein outputting the tail output bits further comprises:
outputting a first tail output bit from the first output branch, X(t); then
outputting a second tail output bit from the second output branch, Y0(t); then
outputting a third tail output bit from the third output branch, X′(t); and then
outputting a fourth tail output bit from the fourth output branch, Y0′(t).
8. The method of claim 3 , wherein when R is ⅓ and outputting the tail output bits comprises:
outputting tail output bits from a first output branch, X(t), and a second output branch, Y0(t), of the first constituent encoder; and
outputting tail output bits from a third output branch, X′(t), and a fourth output branch, Y0′(t), of the second constituent encoder.
9. The method of claim 8 , wherein outputting the tail output bits further comprises:
outputting a first tail output bit from the first output branch, X(t); then:
outputting a second tail output bit from the first output branch, X(t); then
outputting a third tail output bit from the second output branch, Y0(t); then
outputting a fourth tail output branch from the third output branch, X′(t); then
outputting a fifth tail output bit from the third output branch, X′(t); and then
outputting a sixth tail output bit from the fourth output branch, Y0′(t).
10. The method of claim 3 , wherein when R is ¼ and outputting the tail output bits comprises:
outputting tail output bits from a first output branch, X(t), a second output branch, Y0(t), and a third output branch, Y1(t), of the first constituent encoder; and
outputting tail output bits from a fourth X′(t) output branch, a fifth Y0′(t) output branch, and a sixth Y1′(t) output branch of the second constituent encoder.
11. The method of claim 10 , wherein outputting the tail output bits further comprises:
outputting a first tail output bit from the first output branch, X(t); then
outputting a second tail output bit from the first output branch, X(t); then
outputting a third tail output bit from the second output branch, Y0(t); then
outputting a fourth tail output bit from the third output branch, Y1(t); then
outputting a fifth tail output bit from the fourth output branch, X′(t); then
outputting a sixth tail output bit from the fourth output branch, X′(t); then
outputting a seventh tail output bit from the fifth output branch, Y0′(t); and then
outputting an eighth tail output bit from the sixth output branch, Y1′(t).
12. A system for terminating two constituent encoders of a turbo encoder, the system comprising:
a tail bit generator configured to generate tail input bits at each of the two constituent encoders, each of the two constituent encoders comprising a first shift register having a first output that is connected to a second shift register having a second output that is connected to a third shift register having a third output, the tail input bits at each of the two constituent encoders derived after each of the two constituent encoders encodes information bits, the tail input bits derived separately in each of the two constituent encoders from contents of shift registers within the constituent encoder; and
a tail bit terminator configured to output tail output bits from output branches of each of the two constituent encoders during trellis termination,
wherein a first set of tail output bits is generated in a first one of the two constituent encoders from the second and third outputs of the second and third shift registers of the first constituent encoder while a second one of the two constituent encoders is disabled and a second set of tail output bits is generated in the second one of the two constituent encoders from the second and third outputs of the second and third shift registers of the second of the two constituent encoders while the first of the two constituent encoders is disabled.
13. The system of claim 12 , wherein the tail bit terminator is further configured to:
output at least one tail output bit from the first of the two or more constituent encoders more than once; and
output at least one tail output bit from the second of the two or more constituent encoders more than once.
14. The system of claim 12 , wherein the turbo encoder is employed as a coding rate (R) turbo encoder, wherein R is ½, ⅓ or ¼.
15. The system of claim 14 , wherein:
the tail bit generator is further configured to input the tail input bits consecutively at each of the two constituent encoders such that tail input bits are input to the first of the two constituent encoders in different clock cycles than tail input bits input to the second of the two constituent encoders.
16. The system of claim 14 , further comprising a puncturer configured to puncture one or more tail output bits output from each of the constituent encoders.
17. The system of claim 14 , wherein R is ½ and the tail bit terminator is further configured to:
output tail output bits from a first output branch, X(t), and a second output branch, Y0(t), of the first of the two constituent encoders; and
output tail output bits from a third output branch, X′(t), and from a fourth output branch, Y0′(t), of the second of the two constituent encoders.
18. The system of claim 17 , wherein the tail bit terminator is further configured to:
output a first tail output bit from the first output branch, X(t); then
output a second tail output bit from the second output branch, Y0(t); then
output a third tail output bit from the third output branch, X′(t); and then
output a fourth tail output bit from the fourth output branch, Y0′(t).
19. The system of claim 14 , wherein R is ⅓ and the tail bit terminator is further configured to:
output tail output bits from a first output branch, X(t), and a second output branch, Y0(t), of the first constituent encoder; and
output tail output bits from a third output branch, X′(t), and a fourth output branch, Y0′(t), of the second constituent encoder.
20. The system of claim 19 , wherein the tail bit terminator is further configured to:
output a first tail output bit from the first output branch, X(t); then:
output a second tail output bit from the first output branch, X(t); then
output a third tail output bit from the second output branch, Y0(t); then
output a fourth tail output branch from the third output branch, X′(t); then
output a fifth tail output bit from the third output branch, X′(t); and then
output a sixth tail output bit from the fourth output branch, Y0′(t).
21. The system of claim 14 , wherein R is ¼ and the tail bit terminator is further configured to:
output tail output bits from a first output branch, X(t), a second output branch, Y0(t), and a third output branch, Y1(t), of the first constituent encoder; and
output tail output bits from a fourth X′(t) output branch, a fifth Y0′(t) output branch, and a sixth Y1′(t) output branch of the second constituent encoder.
22. The system of claim 21 , wherein the tail bit terminator is further configured to:
output a first tail output bit from the first output branch, X(t); then
output a second tail output bit from the first output branch, X(t); then
output a third tail output bit from the second output branch, Y0(t); then
output a fourth tail output bit from the third output branch, Y1(t); then
output a fifth tail output bit from the fourth output branch, X′(t); then
output a sixth tail output bit from the fourth output branch, X′(t); then
output a seventh tail output bit from the fifth output branch, Y0′(t); and then
output an eighth tail output bit from the sixth output branch, Y1′(t).