Method for a general near optimal turbo code trellis termination
A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.
1. A method for terminating two constituent encoders of a turbo encoder employing a turbo code, the method compromising:
generating tail output bits associated with a turbo code rate (R) in each of the two constituent encoders after at least one of the two constituent encoders encodes information bits,
wherein each of the two constituent encoders comprises a first shift register having a first output that is connected to a second shift register having a second output that is connected to a third shift register having a third output,
wherein a first set of the tail output bits is generated in a first of the two constituent encoders from the second and third outputs of the second and third shift registers of the first of the two constituent encoders while a second of the two constituent encoders is disabled and a second set of the tail output bits is generated in the second of the two constituent encoders from the second and third outputs of the second and third shift registers of the second of the two constituent encoders while the first of the two constituent encoders is disabled.
2. The method of claim 1 , wherein generating the tail output bits comprises generating 12 tail output bits, wherein a first set of 6 tail output bits is generated by clocking the first of the two constituent encoders three times while the second of the two constituent encoders is not clocked and a second set of 6 tail output bits is generated by clocking the second of the two constituent encoders three times while the first of the two constituent encoders is not clocked.
3. The method of claim 1 , wherein the first set of tail output bits is generated from tail input bits derived solely from the second and third outputs of the second and third shift registers of the first of the two constituent encoders.
4. The method of claim 1 , wherein the second set of tail output bits is generated from tail input bits derived solely from the second and third outputs of the second and third shift registers of the second of the two constituent encoders.
5. The method of claim 1 , wherein one tail output bit of the first set of tail output bits is generated solely from the second and third outputs of the second and third shift registers of the first of the two constituent encoders.
6. The method of claim 1 , wherein one tail output bit of the second set of tail output bits is generated solely from the second and third outputs of the second and third shift registers of the second of the two constituent encoders.
7. The method of claim 1 , wherein the tail output bits comprise at least two output bits from each of the two constituent encoders when R is equal to ½, ⅓ or ¼.
8. The method of claim 7 , wherein generating the tail output bits comprises:
puncturing one or more tail output bits such that 1/R tail output bits are transmitted from each of the two constituent encoders.
9. The method of claim 7 , wherein generating the tail output bits comprises:
puncturing one or more tail output bits as follows:
Rate
½
⅓
¼
X(t)
111 000
111 000
111 000
Repeat
Repeat
Y 0 (t)
111 000
111 000
111 000
Y 1 (t)
000 000
000 000
111 000
X′(t)
000 111
000 111
000 111
Repeat
Repeat
Y′ 0 (t)
000 111
000 111
000 111
Y′ 1 (t)
000 000
000 000
000 111
wherein “0” indicates that a bit is punctured and “1” indicates that a bit is transmitted.
10. An apparatus for providing forward error correctable data and operable to communicate data, the apparatus comprising:
a turbo encoder having a turbo code rate (R) for processing data, the turbo encoder comprising two constituent encoders, each of the two constituent encoders encoding information bits and comprising a first shift register having a first output that is connected to a second shift register having a second output that is connected to a third shift register having a third output,
wherein a first set of tail output bits is generated in a first of the of the two constituent encoders from the second and third outputs of the second and third shift registers of the first of the two constituent encoders while a second one of the two constituent encoders is disabled and a second set of tail output bits is generated in the second of the two constituent encoders from the second and third outputs of the second and third shift registers of the second of the two constituent encoders while the first of the two constituent encoders is disabled.
11. The apparatus of claim 10 , wherein the tail output bits comprise at least two output bits from each of the two constituent encoders when R is equal to ½, ⅓ or ¼.
12. The apparatus of claim 10 , wherein the turbo encoder generates 12 tail output bits, wherein a first set of 6 tail output bits is generated by clocking the first of the two constituent encoders three times while the second of the two constituent encoders is not clocked and a second set of 6 tail output bits is generated by clocking the second of the two constituent encoders three times while the first of the two constituent encoders is not clocked.
13. The apparatus of claim 10 , wherein the first set of tail output bits is generated from tail input bits solely derived from the second and third outputs of the second and third shift registers of the first of the two constituent encoders.
14. The apparatus of claim 10 , wherein the second set of tail output bits is generated solely from tail input bits solely derived from the second and third outputs of the second and third shift registers of the second of the two constituent encoders.
15. The apparatus of claim 10 , wherein one tail output bit of the first set of tail output bits is generated solely from the second and third outputs of the second and third shift registers of the first of the two constituent encoders.
16. The apparatus of claim 10 , wherein one tail output bit of the second set of tail output bits is generated solely from the second and third outputs of the second and third shift registers of the second of the two constituent encoders.
17. The apparatus of claim 10 , wherein the turbo encoder further comprises a puncturer for puncturing one or more tail output bits such that 1/R tail output bits are transmitted from each of the two constituent encoders.
18. The system of claim 17 , wherein the puncturer punctures one or more tail output bits as follows:
Rate
½
⅓
¼
X(t)
111 000
111 000
111 000
Repeat
Repeat
Y 0 (t)
111 000
111 000
111 000
Y 1 (t)
000 000
000 000
111 000
X′(t)
000 111
000 111
000 111
Repeat
Repeat
Y′ 0 (t)
000 111
000 111
000 111
Y′ 1 (t)
000 000
000 000
000 111
wherein “0” indicates that a bit is punctured and “1” indicates that a bit is transmitted.