Granted Patent B2

US 7,907,928 · App. 11/983,201 · Granted Mar 15, 2011

Abstract

Claims (62)

1. A combination, comprising:

a unit phase mixer, comprising:

a pull-up path for pulling an output terminal up to a first voltage, said pull-up path comprising a first transistor responsive to a first enable signal, and a series connected second transistor responsive to a first clock signal;

a pull-down path for pulling said output terminal down to a second voltage, said pull-down path comprising a third transistor responsive to a second clock signal, and a series connected fourth transistor responsive to a second enable signal; and

an input buffer configured for skewing said first and second clock signals by different amounts.

2. The combination of claim 1 wherein said input buffer includes a first inverter and a second inverter, each having a different capacitance associated therewith.

3. The combination of claim 1 wherein said input buffer includes a first inverter and a second inverter, each having a different drive capacity associated therewith.

4. The combination of claim 3 wherein said first inverter has a different drive capacity associated with p-channel devices than the drive capacity associated with n-channel devices, and wherein said second inverter has the same drive capacity associated with both p-channel and n-channel devices.

5. The combination of claim 1 additionally comprising an inverter for receiving said second enable signal and inverting said second enable signal to produce said first enable signal or for receiving said first enable signal and inverting said first enable signal to produce said second enable signal.

6. The combination of claim 1 additionally comprising:

another unit phase mixer comprising:

another pull-up path for pulling said output terminal up to said first voltage, said another pull-up path comprising a fifth transistor responsive to a third enable signal, and a series connected sixth transistor responsive to a third clock signal;

another pull-down path for pulling said output terminal down to said second voltage, said another pull-down path comprising a seventh transistor responsive to a fourth clock signal, and a series connected eighth transistor responsive to a fourth enable signal; and

another input buffer for skewing said third and fourth clock signals by different amounts.

7. The combination of claim 6 wherein said first, second, third, and fourth enable signals are based on weighting factors.

8. A unit phase mixer, comprising:

a first circuit portion comprising a first input for receiving a first clock signal and a first plurality of transistors for generating a first skewed clock signal and a second skewed clock signal in response to said first clock signal;

a second circuit portion comprising a second input for receiving an enable signal, a third input for receiving an inverted enable signal, and a second plurality of transistors for enabling said first circuit portion to generate said first skewed clock signal and said second skew clock signal, wherein said enabling is responsive to said enable signal and said inverted enable signal; and

a third circuit portion comprising a third plurality of transistors for generating an output signal in response to said first skewed clock signal and said second skewed clock signal, said output signal being available at an output terminal of said unit phase mixer.

9. The unit phase mixer of claim 8 , wherein said third circuit portion further comprises a fourth input for receiving a first feed-forward signal and a fifth input for receiving a second feed-forward signal, said third circuit portion being additionally responsive to said first feed-forward signal and said second feed-forward signal for generating said output signal.

10. The unit phase mixer of claim 8 , wherein said third plurality of transistors comprise a pull-up path for pulling said output signal up to a first voltage and a pull-down path for pulling said output signal down to a second voltage.

11. The unit phase mixer of claim 10 , wherein said pull-up path has a first transistor responsive to said first skewed clock signal and said pull-down path has a second transistor responsive to said second skewed clock signal.

12. The unit phase mixer of claim 8 , further comprising a second output terminal for outputting said first skewed clock signal and a third output terminal for outputting said second skewed clock signal.

13. The unit phase mixer of claim 8 , wherein said first plurality of transistors comprises one or more p-channel transistors and one or more n-channel transistors.

14. The unit phase mixer of claim 13 , wherein said first plurality of transistors has a drive capacity associated with said one or more p-channel transistors that is different from the drive capacity associated with said one or more n-channel transistors.

15. A method of mixing two signals, comprising:

inputting a first regulation signal and a first enable signal to a pull-up path for pulling an output terminal up to a first voltage;

inputting a second regulation signal and a second enable signal to a pull-down path for pulling said output terminal down to a second voltage; and

outputting a signal available at said output terminal in response to the operation of said pull-up and pull-down paths.

16. The method of claim 15 , wherein said first regulation signal has a longer duty cycle than said second regulation signal.

17. The method of claim 15 , wherein the rising edge of said first regulation signal has a faster slew rate than the rising edge of said second regulation signal.

18. The method of claim 15 , wherein the falling edge of said first regulation signal has a slower slew rate than the falling edge of said second regulation signal.

19. The method of claim 15 , wherein the said pull-up path and said pull-down path are operated such that currents between said first and second voltages are eliminated.

20. The method of claim 15 , wherein said first enable signal and said second enable signal are based on desired weights.

21. A method for phase mixing clock signals, comprising:

receiving a first clock signal and a second clock signal, wherein said first clock signal and said second clock signal have a phase difference there between;

generating a first skewed clock signal and a second skewed clock signal based on said first clock signal, wherein said first skewed clock signal and said second skewed clock signal are skewed by different amounts;

generating a third skewed clock signal and a fourth skewed clock signal based on said second clock signal, wherein said third skewed clock signal and said fourth skewed clock signal are skewed by different amounts; and

generating an output clock signal based on said first, second, third, and fourth skewed clock signals, wherein the phase of said output clock signal is responsive the phase difference of said first clock signal and said second clock signal.

22. The method of claim 21 , further comprising:

receiving a plurality of enable signals based on weighting factors; and

generating a plurality of inverted enable signals based on said plurality of enable signals, wherein said plurality of enable signals and said plurality of inverted enable signals enable generation of said output clock signal.

23. The method of claim 21 , wherein said first clock signal and said second clock signal are generated from the same clock signal.

24. A memory device, comprising:

an array of memory cells; and

a plurality of peripheral devices for reading data out of said array of memory cells, said peripheral devices including a phase mixer, comprising:

a first pull-up path for pulling an output terminal up to a first voltage, said first pull-up path comprising a first transistor responsive to a first enable signal, and a series connected second transistor responsive to a first clock signal;

a first pull-down path for pulling said output terminal down to a second voltage, said first pull-down path comprising a third transistor responsive to a second clock signal, and a series connected fourth transistor responsive to a second enable signal;

a first input buffer for skewing said first and second clock signals by different amounts;

a second pull-up path for pulling said output terminal up to said first voltage, said second pull-up path comprising a fifth transistor responsive to a third enable signal, and a series connected sixth transistor responsive to a third clock signal;

a second pull-down path for pulling said output terminal down to said second voltage, said second pull-down path comprising a seventh transistor responsive to a fourth clock signal, and a series connected eighth transistor responsive to a fourth enable signal; and

a second input buffer for skewing said third and fourth clock signals by different amounts.

25. A system, comprising:

a processor;

a memory device;

a bus for interconnecting said processor and said memory device, said memory device comprising an array of memory cells and a plurality of peripheral devices for reading data out of said array of memory cells, said peripheral devices including a phase mixer, comprising:

a first pull-up path for pulling an output terminal up to a first voltage, said first pull-up path comprising a first transistor responsive to a first enable signal, and a series connected second transistor responsive to a first clock signal;

a first pull-down path for pulling said output terminal down to a second voltage, said first pull-down path comprising a third transistor responsive to a second clock signal, and a series connected fourth transistor responsive to a second enable signal;

a first input buffer for skewing said first and second clock signals by different amounts;

a second pull-up path for pulling said output terminal up to said first voltage, said second pull-up path comprising a fifth transistor responsive to a third enable signal, and a series connected sixth transistor responsive to a third clock signal;

a second pull-down path for pulling said output terminal down to said second voltage, said second pull-down path comprising a seventh transistor responsive to a fourth clock signal, and a series connected eighth transistor responsive to a fourth enable signal; and

a second input buffer for skewing said third and fourth clock signals by different amounts.

Assignments (7)