Bus relay device and bus control system including plurality of bus masters, bus slave, interconnect section, and bridge section
View Patent ↗In the conventional bus control system, the interconnect section and the bridge section have the arbitration function. Meanwhile, the interconnect section and the bridge section were designed by different designers. Accordingly, a large number of man-hours are needed not only for designing the bridge section but also for inspecting the bridge section. To solve this problem, provided is a system comprising a plurality of bus masters coupled to a high speed bus and outputting first control signals respectively via the high speed bus; a bus slave coupled to a low speed bus and receiving a second control signal via the low speed bus; an interconnect section receiving the first control signals via the high speed bus, selecting one of the first control signals, and converting the selected one of the first signals into a third control signal relative to the second control signal; and a bridge section coupled to the low speed bus, converting the third control signal into the second control signal, and outputting the second control signal to the low speed bus. With this configuration, the bus arbitrations can be collectively controlled in the interconnect section alone. In addition, a circuit size can be reduced.
1. A system comprising:
a plurality of bus masters coupled to a bus to output first control signals via said bus;
a bus slave coupled to another bus to receive a second control signal via said another bus;
an interconnect section coupled to receive said first control signals via said bus, wherein said interconnect section selects one of said first control signals, and converts said selected one of said first signals into a third control signal corresponding to said second control signal; and
a bridge section coupled to said interconnect section to convert said third control signal into said second control signal, to output said second control signal to said another bus, wherein a bit width of said third control signal indicating an address is equal to a bit width of each of said first control signals indicating an address.
2. The system according to claim 1 , wherein
each of said masters outputs a plurality of said first control signals.
3. The system according to claim 1 , wherein
said interconnect section selects said one of said first control signals in accordance with an order of priority among said bus masters and an order of priority among said first control signals.
4. The system according to claim 1 , wherein
said bridge section converts said third control signal into said second control signal by performing a bus protocol conversion of said third control signal.
5. The system according to claim 1 , wherein
said bus comprises a high speed bus and said another bus comprises a low speed bus.
6. The system according to claim 3 , wherein
said interconnect section comprises a register storing information of said order of priority among said bus masters and said order of priority of among said first control signals.
7. The system according to claim 6 , wherein
said information stored in said register is rewritable by a processor.
8. A system, comprising:
a plurality of bus masters coupled to a bus to output first control signals via said bus;
a bus slave coupled to another bus to receive a second control signal via said another bus;
an interconnect section coupled to receive said first control signals via said bus, wherein said interconnect section selects one of said first control signals, and converts said selected one of said first signals into a third control signal corresponding to said second control signal; and
a bridge section coupled to said interconnect section to convert said third control signal into said second control signal, to output said second control signal to said another bus, wherein
a bit width of said third control signal indicating an address is wider than a bit width of said second control signal indicating an address.
9. A system comprising:
a first bus master coupled to a first bus to output a first control signal group including a plurality of control signals onto said first bus;
a second bus master coupled to said first bus to output a second control signal group including a plurality of control signals onto said first bus;
an interconnect section coupled between said first bus and a second bus to receive said first and second control signal groups respectively and to output a third control signal group including a plurality of signals onto said second bus;
a bridge section coupled between said second bus and a third bus to receive said third control signal group and to output a fourth control signal group including a plurality of signals onto said third bus without performing a selecting operation for said third control signal group; and
a bus slave coupled to said third bus to receive said fourth control signal group.
10. The system according to claim 9 , wherein said number of signals included in said third control signal group is larger than a number of signals included in said fourth control signal group.
11. The system according to claim 9 , wherein said number of signals included in said first control signal group is equal to said number of signals included in said second control signal group.
12. The system according to claim 9 , wherein said third control signal group includes a write enable signal.
13. The system according to claim 9 , wherein a specification of said second bus is different from a specification of said first bus.
14. The system according to claim 9 , wherein a specification of said second bus is different from each of specifications of said first and third buses.
15. The system according to claim 9 , wherein said interconnect section selects one of said first and second control signal groups and converts said selected one of said first and second control signal groups into said third control signal group.
16. The system according to claim 9 , wherein said bridge section converts said third control signal group into said fourth control signal group.
17. The system according to claim 9 , wherein a number of signals included in said third control signal group is smaller than a number of signals included in said first control signal group and a number of signals included in said second control signal group.