Semiconductor apparatus having a large-size bus connection
View Patent ↗In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
1. A semiconductor apparatus having circuit components, comprising:
a first bus interconnecting the circuit components;
a second bus interconnecting the circuit components; and
a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,
the second bus having a size larger than a size of the first bus,
wherein the first bus is provided for transmission of the signal between the circuit components before formation of the second bus, and, when the semiconductor apparatus operates before the formation of the second bus, the signal is transmitted on the first bus from one of the circuit components to another.
2. A semiconductor apparatus having circuit components, comprising:
a first bus interconnecting the circuit components;
a second bus interconnecting the circuit components; and
a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,
the switching unit being configured such that the first bus is selected only when a wafer test is conducted before formation of the second bus, and the second bus is selected at any time the semiconductor apparatus operates after the wafer test is conducted.
3. The semiconductor apparatus according to claim 1 , wherein the first bus and the second bus are provided to transmit a same signal from one of the circuit components to another.
4. The semiconductor apparatus according to claim 1 , wherein the first bus and the second bus are provided to transmit at least one of an address signal, a data signal, a control signal and a clock signal between the circuit components.
5. A semiconductor apparatus having circuit components, comprising:
a first bus interconnecting the circuit components;
a second bus interconnecting the circuit components; and
a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,
the second bus having a size larger than a size of the first bus,
wherein the switching unit is configured such that the second bus is always selected when the semiconductor apparatus operates after the formation of the second bus in the semiconductor apparatus.
6. The semiconductor apparatus according to claim 1 , wherein the switching unit is provided to establish electrical connection between the circuit components by only the selected one of the first bus and the second bus.
7. The semiconductor apparatus according to claim 1 , wherein the switching unit is provided with a programmable device.
8. The semiconductor apparatus according to claim 1 , wherein the second bus includes signal line portions having a substantially equal length.
9. A semiconductor apparatus having circuit components, comprising:
a first wiring layer provided on a chip and including a number M of first electrodes, the M first electrodes being connected to the circuit components via a first bus; and
a second wiring layer provided above the first wiring layer and including a number N of second electrodes, the N second electrodes being connected to the circuit components via a second bus, the second bus having a size larger than a size of the first bus,
wherein the semiconductor apparatus is configured such that a clock signal is received at each of the first electrodes and the second electrodes and the conditions M>N.box-solid.1 are met,
wherein the circuit components includes respective receiver units each of which is connected to one of the M first electrodes, and, when a select signal is set at a first level, the clock signal received at each first electrode is transmitted through the first wiring layer to corresponding one of the circuit components, and, when the select signal is set at a second level, the clock signal received at each second electrode is transmitted through the second wiring layer to corresponding one of the circuit components.