Pad invariant FPGA and ASIC devices
View Patent ↗A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.
1. A semiconductor device, comprising:
a plurality of pads having first predetermined positions;
a first layer including a plurality of circuit blocks having second predetermined positions, at least one of said circuit blocks coupled to one of said pads; and
a second layer positioned above or below the first layer including a memory array coupled to one or more of said circuit blocks, wherein the second layer comprises a plurality of configurations with the same first and second predetermined positions of pads and circuit blocks, respectively, and wherein
a first fabricating configuration comprises a user programmable memory array, and
a second fabricating configuration comprises a mask programmable memory array in lieu of the user programmable memory array.
2. The method of claim 1 , wherein the circuit blocks include programmable logic circuits and the memory array comprises memory elements, at least one of the memory elements is coupled to one programmable logic circuit to configure the programmable logic circuit.
3. The method of claim 1 , wherein said memory array configuration comprises a field programmable memory array to form an FPGA.
4. The method of claim 1 , wherein said memory array configuration comprises a mask programmable metal pattern to form an ASIC.
5. The method of claim 1 , wherein one pad is coupled to power or ground supply voltage.
6. The method of claim 1 , wherein one pad is coupled to an Input/Output (I/O) circuit block in the first layer, the I/O having an I/O characteristic invariant to memory array configurations.
7. The method of claim 1 , wherein the pads are coupled to leads of a package.
8. The method of claim 1 , wherein the first layer includes one or more input buffers to receive data from one or more of said pads to program the memory array in a said memory array configuration.
9. The method of claim 1 , wherein a said memory array configuration comprises one or more of: fuses, antifuses, SRAM cells, DRAM cells, metal optional links, EPROMs, EEPROMs, flash, resistance modulating elements, magneto-electric elements, photo-electric elements and ferro-electric elements.
10. The method of claim 1 , wherein the first layer comprises circuits to request configuration data from an external storage device for a said memory array configuration.
11. A three dimensional semiconductor device, comprising:
a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device;
a plurality of pads surrounding the circuit blocks; and
a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabrication configurations, each configuration fabricated with the same predetermined positions of the circuit blocks and pads, and wherein
a first fabricating configuration comprises a user programmable memory array, and
a second fabricating configuration comprises a mask programmable memory array in lieu of the user programmable memory array.