IP Library Granted Patent US 7,645,661
Granted Patent B2
US 7,645,661 · App. 11/987,191 · Granted Jan 12, 2010

Semiconductor device

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Quick Facts
Patent No.
US 7,645,661
App. No.
11/987,191
Granted
Jan 12, 2010
Kind
B2
Abstract

A semiconductor device manufactured by forming a plurality of first trenches in each of which a trench gate is formed, in an epitaxial layer of a first conductivity type; implanting an impurity of a second conductivity type into a part beneath each of the first trenches to form a first column region; and implanting an impurity of the second conductivity type into a part beneath a base region formed between the first trenches to form a second column region. The first and second column regions are formed with an impurity concentration such that a total depletion charge in the regions is substantially equal to a depletion charge in the epitaxial layer.

Claims (29)

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of first trenches in each of which a trench gate is to be formed, in an epitaxial layer of a first conductivity type;

implanting an impurity of a second conductivity type into a part beneath each of the first trenches to form a first column region; and

implanting an impurity of the second conductivity type into a part beneath a base region formed between the first trenches to form a second column region,

wherein the first and the second column regions are formed with an impurity concentration such that a total depletion charge in the first and the second column regions is substantially equal to a depletion charge in the epitaxial layer.

2. The method of manufacturing a semiconductor device of claim 1 , wherein the second column region is formed beneath a second trench formed in a surface of the base region.

3. A method of manufacturing a semiconductor device, comprising:

forming a first trench in a semiconductor layer of a first conductivity type;

implanting an impurity of a second conductivity type in the semiconductor layer through the first trench to form a first column region;

forming a second trench in the semiconductor layer;

implanting an impurity of the second conductivity type in the semiconductor layer through the second trench to form a second column region; and

filling a conductive material in the second trench.

4. The method of manufacturing a semiconductor device of claim 3 , wherein the first column region is separate from the first trench.

5. The method of manufacturing a semiconductor device of claim 3 , wherein the first column region has a continuous form.

6. The method of manufacturing a semiconductor device of claim 3 , wherein the first column region comprises a plurality of separate regions.

7. The method of manufacturing a semiconductor device of claim 3 , further comprising a base region of the second conductivity type formed in the semiconductor layer and a source region of the first conductivity type formed in the base region.

8. The method of manufacturing a semiconductor device of claim 7 , wherein the second column region is continuous with the base region.

9. The method of manufacturing a semiconductor device of claim 7 , wherein the second column region is separate from the base region.

10. The method of manufacturing a semiconductor device of claim 3 , wherein the second column region has a continuous form.

11. The method of manufacturing a semiconductor device of claim 3 , wherein the second column region comprises a plurality of separate regions.

12. The method of manufacturing a semiconductor device of claim 3 , wherein each of the first and the second column regions has a continuous form.

13. The method of manufacturing a semiconductor device of claim 3 , wherein each of the first and the second column regions comprises a plurality of separate regions.

14. The method of manufacturing a semiconductor device of claim 7 , wherein the conductive material is connected to both the base region and the source region.

15. The method of manufacturing a semiconductor device of claim 1 , further comprising forming said base region above said epitaxial layer of said first conductivity type.

16. The method of manufacturing a semiconductor device of claim 15 , further comprising orienting vertically said first and second column regions relative to a substrate.

17. The method of manufacturing a semiconductor device of claim 2 , further comprising locating the second trench located between said first trenches with trench gates, the base layer being exposed at a location of the second trench, and a source electrode being located thereon.

18. The method of manufacturing a semiconductor device of claim 3 , further comprising forming said base region above said semiconductor layer of said first conductivity type.

19. The method of manufacturing a semiconductor device of claim 18 , further comprising orienting vertically said first and second column regions.

20. The method of manufacturing a semiconductor device of claim 6 , further comprising locating the second trench between said separate regions of said first column region, a base layer being exposed at the location of the second trench, and a source electrode being located thereon.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0423 →