IP Library Granted Patent US 7,622,762
Granted Patent B2
US 7,622,762 · App. 12/000,396 · Granted Nov 24, 2009

Nonvolatile semiconductor memory and method for fabricating the same

Assignee: Kabushiki Kaisha Toshiba
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,622,762
App. No.
12/000,396
Granted
Nov 24, 2009
Kind
B2
Abstract

A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

Claims (38)

1. A method for fabricating a nonvolatile semiconductor memory comprising:

forming a barrier insulator film on a semiconductor substrate;

subsequently forming a first interlayer insulator film on the barrier insulator film;

delineating a data transfer line contact and a source line contact in the first interlayer insulator film;

forming a trench in the first interlayer insulator film to bury a source line and a passing interconnect;

depositing a first barrier metal in the trench;

depositing a first metallic material to fill the trench;

etching back the first metallic material to form the data transfer line contact, the source line contact, a source line, and a passing interconnect in the first interlayer insulator film;

depositing a second interlayer insulator film on the first interlayer insulator film;

delineating for a via contact in second interlayer insulator film;

etching the second interlayer insulator film so as to extend the top of the data transfer line contact;

depositing a second barrier metal on the top of the data transfer line contact;

filling a second metallic material on the second barrier metal;

etching back the second metallic material; and

forming the via contact in second interlayer insulator film.

2. The method of claim 1 , wherein,

delineating for the data transfer line contact and the source line contact and etching the barrier insulator film are performed simultaneously.

3. The method of claim 1 , wherein,

delineating for the data transfer line contact and the source line contact, and etching the barrier insulator film are performed separately.

4. A method for fabricating a nonvolatile semiconductor memory, comprising:

forming a barrier insulator film on a semiconductor substrate;

subsequently forming a first interlayer insulator film on the barrier insulator film;

delineating a data transfer line contact and a source line contact simultaneously in the first interlayer insulator film;

forming a trench in the first interlayer insulator film to bury the data transfer line contact and the source line contact;

depositing and filling one of phosphorus or arsenic doped polycrystalline silicon in the trench;

etching back the doped polycrystalline silicon to bury the data transfer line contact and the source line contact in the first interlayer insulator film;

forming another trench in the first interlayer insulator film to bury a source line, a passing interconnect, and a data transfer line interconnect;

depositing a first barrier metal in the another trench;

depositing a first metallic material to fill the another trench;

etching back the first metallic material;

forming the source line, the passing interconnect, and the data transfer line interconnect filled in the first interlayer insulator film;

depositing a second interlayer insulator film on the first interlayer insulator film;

delineating for a via contact in the second interlayer insulator film;

etching the second interlayer insulator film so as to extend the top of the data transfer line interconnect;

depositing a second barrier metal on the top of the data transfer line interconnect;

filling the second metallic material on the second barrier metal;

etching back the second metallic material; and

forming the via contact in the second interlayer insulator film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2020
From: KIOXIA CORPORATION
To: KATANA SILICON TECHNOLOGIES LLC
Reel/Frame 052243/0355 →
Priority Claims (1)
JP P2003-197095 · Jul 15, 2003 · national
Continuity (2)
Division 1089013200 · Jul 14, 2004
Related Publication 20080122098A1 · May 29, 2008