Nonvolatile semiconductor memory having suitable crystal orientation
View Patent ↗An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers; and a charge storage layer formed in the insulating film. A direction from the first N-type diffusion layer to the second N-type diffusion layer is the same as a crystal orientation <100> of the P-type silicon layer. At the time of rewriting, the hot holes go over a potential barrier of the insulating film to be injected into the charge storage layer.
1. A nonvolatile semiconductor memory of an NMOS transistor type, comprising:
first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain, a direction from the first N-type diffusion layer to the second N-type diffusion layer being the same as a crystal orientation <100> of the P-type silicon layer;
a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers; and
a charge storage layer formed in the insulating film to store electric charges, said charge storage layer being injected with a hot hole beyond a potential barrier of the insulating film, at a time of rewriting data.
2. The memory according to claim 1 , wherein at the time of rewriting the data, a negative potential relative to a potential of the P-type silicon layer is applied to the gate electrode, and a positive potential relative to a potential of the P-type silicon layer is applied to at least one of the first and second N-type diffusion layers.
3. The memory according to claim 2 , wherein at the time of rewriting the data, the positive potential is applied to both of the first and second N-type diffusion layers.
4. The memory according to claim 1 , wherein a surface of the P-type silicon layer comprises a crystal plane (100).
5. The memory according to claim 1 , wherein the charge storage layer comprises a floating gate.
6. The memory according to claim 5 , wherein the floating gate is arranged so that the gate electrode partially overlaps the floating gate and a portion of the gate electrode is provided on the channel region via the insulating film.
7. The memory according to claim 1 , wherein
the insulating film comprises an oxide film and
the charge storage layer comprises a nitride film.
8. The memory according to claim 1 , further comprising a selection gate,
wherein the charge storage layer is placed between the gate electrode and the channel region as well as between the gate electrode and the selection gate.
9. A nonvolatile semiconductor memory of an NMOS transistor type, comprising:
first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain, a direction from the first N-type diffusion layer to the second N-type diffusion layer being the same as a crystal orientation <100> of the P-type silicon layer;
a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers;
a charge storage layer formed in the insulating film between the channel region and the gate electrode and having electric charges stored therein; and
a potential applying unit which, at a time of rewriting data, applies a negative potential relative to a potential of the P-type silicon layer to the gate electrode and applies a positive potential relative to a potential of the P-type silicon layer, to at least one of the first and second N-type diffusion layers.
10. The memory according to claim 9 , wherein at the time of rewriting the data, the potential applying unit applies the positive potential to both of the first and second N-type diffusion layers.
11. A method of operating a nonvolatile semiconductor memory, comprising:
applying a negative potential relative to a potential of a P-type silicon layer to a gate electrode of a semiconductor memory cell, at a time of rewriting data; and
at a same time as said applying, applying a positive potential relative to a potential of the P-type silicon layer, to at least one of first and second N-type diffusion layers of said semiconductor memory cell, a direction from the first N-type diffusion layer to the second N-type diffusion layer being the same as a crystal orientation <100> of the P-type silicon layer.
12. The method as claimed in claim 11 ,
wherein said first and second N-type diffusion layers are formed in said P-type silicon layer as a source and a drain; and
said gate electrode is formed on a channel region with an insulating film interposed therebetween and the channel region is sandwiched between the first and second N-type diffusion layers.
13. The method as claimed in claim 12 , wherein said memory cell further comprises:
a charge storage layer which is formed in the insulating film between the channel region and the gate electrode.
14. A method of operating a nonvolatile semiconductor memory, comprising:
applying a negative potential relative to a potential of a P-type silicon layer to a gate electrode of a semiconductor memory cell, at a time of rewriting data; and
at a same time as said applying, applying a positive potential relative to a potential of the P-type silicon layer, to at least one of first and second N-type diffusion layers of said semiconductor memory cell.
15. The method as claimed in claim 14 , wherein at the time of rewriting, electrons flow in a direction from the first N-type diffusion layer toward the second N-type diffusion layer, and a direction in which the electrons flows is the same as the crystal orientation <100> of the P-type silicon layer.