IP Library Granted Patent US 7,663,427
Granted Patent B2
US 7,663,427 · App. 12/000,612 · Granted Feb 16, 2010

Booster circuit

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Quick Facts
Patent No.
US 7,663,427
App. No.
12/000,612
Granted
Feb 16, 2010
Kind
B2
Abstract

A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Claims (62)

1. A charge pump type booster circuit generating a positive or negative boosted output voltage by switching booster paths one by one, the charge pump type booster circuit comprising:

a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor,

wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and another booster path,

wherein the plurality of booster paths includes:

a first booster path outputting a first output voltage obtained by boosting an input voltage, the first booster path including at least a first booster capacitor and a third booster capacitor; and

a second booster path outputting a second output voltage obtained by boosting the input voltage, the second booster path including at least a second booster capacitor,

wherein the first booster path further comprises a first switch group including:

a first switch unit between a first power supply potential and the first booster capacitor;

a second switch unit between the first booster capacitor and the third booster capacitor; and

a third switch unit between the third booster capacitor and an output terminal.

2. The booster circuit according to claim 1 , wherein the booster circuit alternately outputs the first output voltage and the second output voltage.

3. The booster circuit according to claim 1 , wherein the second booster capacitor is charged based on an output from the first booster capacitor.

4. The booster circuit according to claim 1 , wherein a voltage boosted by the second booster capacitor is output as the second output voltage.

5. The booster circuit according to claim 1 , wherein a number of capacitor included in the second booster path is less than a number of capacitor included in the first booster path.

6. The booster circuit according to claim 1 , wherein the second booster path further includes a second switch group including:

a fourth switch unit between the first power supply potential and the second booster capacitor; and

a fifth switch unit between the second booster capacitor and the output terminal.

7. The booster circuit according to claim 6 , wherein each of first terminals of the first and third booster capacitors is connected to the first power supply potential and each of second terminals of the first and third booster capacitors is connected to a second power supply potential when the second output voltage is output from the second booster path.

8. The booster circuit according to claim 6 , wherein a second terminal of the second booster capacitor is connected to a second power supply potential when the first output voltage is output from the first booster path.

9. The booster circuit according to claim 7 , wherein the first switch group further includes a second and sixth switch units between the first and third booster capacitors, the second switch unit is at a side of the first booster capacitor and the sixth switch unit is at a side of the third booster capacitor.

10. The booster circuit according to claim 9 , wherein a first terminal of the second booster capacitor is connected to a node between the second switch unit and the sixth switch unit.

11. The booster circuit according to claim 9 , wherein the second and sixth switch units are in an OFF-state when the second output voltage is output from the second booster path.

12. The booster circuit according to claim 1 , wherein a level of the first output voltage is substantially the same with a level of the second output voltage.

13. The booster circuit according to claim 1 , wherein each of the first and second output voltages is gained by boosting the input voltage three or more times.

14. The booster circuit according to claim 1 , wherein each of the first and second output voltages is gained by boosting the input voltage by a negative multiple having an absolute value of two or more.

15. The booster circuit according to claim 1 , further comprising:

an output terminal that is common among the plurality of booster paths; and

a smoothing capacitor connected to the output terminal and charged based on the positive or negative boosted output voltage.

16. A booster circuit comprising:

a first output path boosting an input voltage N (N is a positive or negative integer having an absolute value of two or more) times, coupled between an input terminal and an output terminal; and

a second output path boosting the input voltage N times, coupled between the input terminal and the output terminal,

wherein

the booster circuit outputs a first boosted voltage output from the first output path and a second boosted voltage output from the second output path alternately to the output terminal, based on a control signal transmitted from a control circuit, and

wherein

the second boosted voltage is set based on a boosted voltage gained by boosting the input voltage M (M is a positive or negative integer having an absolute value smaller than that of N) times when the first output voltage is output from the booster circuit.

17. A booster circuit comprising:

a first capacitor;

a second capacitor;

a third capacitor;

a first booster circuit, which has a first voltage boost path including the first capacitor and the third capacitor, to output a first boosted voltage, by boosting a first voltage potential charged by the first capacitor with an input voltage, and by boosting a second voltage potential charged by the third capacitor with a boosted first voltage potential, the first booster circuit charging the first boosted voltage potential to the second capacitor; and

a second booster circuit, which has a second voltage boost path including the second capacitor to output a second boosted voltage, by boosting the first voltage potential charged by the second capacitor with the input voltage, the second booster circuit charging the input voltage to the first and third capacitors.

18. The booster circuit as claimed in claim 17 ,

wherein the first capacitor and the third capacitor are connected in series between an input terminal and an output terminal to output the first boosted voltage at the output terminal, and

wherein the second capacitor is connected between the input terminal and the output terminal to output the second boosted voltage at the output terminal.

19. The booster circuit as claimed in claim 18 ,

wherein the first booster circuit boosts the first voltage potential and the second voltage potential and charges the first voltage potential at a same time, and

wherein the second booster circuit boosts the first voltage potential and the second voltage potential, and charges the input voltage at a same time.

20. A boost circuit, comprising:

a first capacitor;

a second capacitor;

a third capacitor;

a first switch coupled between an input terminal and the first capacitor;

a second switch coupled between the first capacitor and a predetermined power source;

a third switch coupled between the input terminal and the third capacitor;

a fourth switch coupled between the third capacitor and the predetermined power source;

a fifth switch coupled between the input terminal and the second capacitor;

a sixth switch coupled between the second capacitor and an output terminal;

a seventh switch coupled between the input terminal and the first capacitor;

an eighth switch coupled between the first and second capacitors;

a ninth switch coupled between the second capacitor and the predetermined power source;

a tenth switch coupled between the second and third capacitors; and

an eleventh switch coupled between the third capacitor and the output terminal.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2007
From: FUJIWARA, HIROFUMI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020296/0292 →