Method for manufacturing bipolar transistor
View Patent ↗A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.
1. A method for manufacturing a bipolar transistor comprising:
forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity;
implanting ions of a second conductivity in the first well to form a third well;
forming and patterning a conductive layer on the third well region to form a base electrode pattern;
forming a spacer on a sidewalls of the base electrode pattern;
implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and
performing a diffusion process to form a base region adjacent to the emitter region.
2. The method according to claim 1 , further comprising
forming and patterning a dielectric layer on an entire surface of the substrate after forming the base region;
forming a plurality of contact holes exposing the base electrode pattern, the emitter region, and the collector region; and
forming a conductive layer in the contact holes to form contact plugs in contact with the emitter electrode, the base electrode pattern, and the collector region.
3. The method according to claim 1 , wherein the conductive layer comprises a polysilicon layer containing a second conductivity type dopant.
4. The method according to claim 3 , wherein the first conductivity is n-type, and the second conductivity is p-type.
5. The method according to claim 1 , wherein the first conductivity is n-type, and the second conductivity is p-type.
6. The method according to claim 1 , further comprising implanting n+ ions in the conductive layer.
7. The method according to claim 1 , wherein the base electrode pattern comprises at least two parallel portions spaced apart from each other.
8. The method according to claim 1 , wherein spacers secure a distance between the base region and the emitter region that allows a resistance of the base region to be reduced.
9. The method according to claim 1 , wherein after the diffusion process, the base region has a depth similar to that of the emitter region.
10. The method according to claim 1 , further comprising, after forming the base region, forming a dielectric layer on an entire surface of the substrate and patterning the dielectric layer.
11. The method according to claim 10 , further comprising forming a plurality of contact holes in the dielectric layer exposing the base electrode pattern, the emitter region, and the collector region.
12. The method according to claim 11 , further comprising forming contact plugs in the contact holes, the contact plugs being in contact with the emitter electrode, the base electrode pattern, and the collector region.