IP Library Granted Patent US 7,855,407
Granted Patent B2
US 7,855,407 · App. 12/002,124 · Granted Dec 21, 2010

CMOS image sensor and method for manufacturing the same

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Quick Facts
Patent No.
US 7,855,407
App. No.
12/002,124
Granted
Dec 21, 2010
Kind
B2
Abstract

Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.

Claims (31)

1. A CMOS image sensor, comprising:

a semiconductor substrate having a photosensor unit and a device isolating implant area comprising a first ion implant area and a complementary second ion implant area within the first ion implant area, a first depletion layer at a junction location of the first ion implant area and the second ion implant area, and a second depletion layer at a junction location of the second ion implant area and the semiconductor substrate, wherein the second depletion layer has a greater thickness than the first depletion layer;

a device isolating layer in a signal processing unit on the semiconductor substrate;

a photodiode in the photosensor unit; and

transistors in the signal processing unit.

2. The CMOS image sensor according to claim 1 , wherein the first ion implant area comprises a p-type dopant, and the second ion implant area comprises an n-type dopant.

3. The CMOS image sensor according to claim 1 , wherein the semiconductor substrate comprises a p-type epitaxial silicon layer.

4. The CMOS image sensor according to claim 1 , further comprising a contact electrode connected to the second ion implant area, configured to apply a reverse voltage to the second ion implant area.

5. The CMOS image sensor according to claim 1 , wherein the second ion implant area is connected to a power source.

6. The CMOS image sensor according to claim 1 , wherein the second ion implant area is surrounded by the first ion implant area.

7. The CMOS image sensor according to claim 1 , wherein the photodiode is divided into at least two areas by the device isolating implant area.

8. The CMOS image sensor according to claim 1 , wherein the photosensor unit comprises photodiodes for at least two unit pixels, the respective unit pixels comprising at least two transistors.

9. The CMOS image sensor according to claim 8 , wherein the device isolating implant area is formed at boundary between adjacent unit pixels.

10. A method for manufacturing a CMOS image sensor having a photosensor unit and a signal processing unit, comprising the steps of: forming a device isolating layer in the signal processing unit in a semiconductor substrate; forming a preliminary device isolating implant area in the photosensor unit by forming a first ion implant area in the semiconductor substrate; completing a device isolating implant area by forming a complementary second ion implant area within the first ion implant area, a first depletion layer at a junction location of the first ion implant area and the second ion implant area, and a second depletion layer at a junction location of the second ion implant area and the semiconductor substrate, wherein the second depletion layer has a greater thickness than the first depletion layer; and forming a photodiode in the photosensor unit and transistors in the signal processing unit.

11. The method according to claim 10 , further comprising:

forming an insulating film on the photodiode and the transistors;

forming a contact hole in the insulating film exposing a surface of the second ion implant area; and

forming a contact in the contact hole electrically connected to the second ion implant area.

12. The method according to claim 10 , wherein a depletion layer of the device isolating implant area becomes deeper when a reverse voltage is applied to the second ion implant area.

13. The method according to claim 10 , wherein the first ion implant area comprises a p-type dopant, and the second ion implant area comprises an n-type dopant.

14. The method according to claim 11 , wherein a reverse voltage is applied to the contact.

15. The method according to claim 11 , wherein a power supply voltage is applied to the contact.

16. The method according to claim 10 , wherein the photosensor unit comprises photodiodes in at least two unit pixels, wherein each unit pixel comprises at least two transistors.

17. The method according to claim 16 , wherein the device isolating implant area is at the boundary between adjacent unit pixels.

18. A CMOS image sensor, comprising:

a semiconductor substrate having a photosensor unit and a device isolating implant area comprising a first ion implant area and a complementary second ion implant area within the first ion implant area, wherein the first ion implant area comprises a p-type dopant, and the second ion implant area comprises an n-type dopant;

a device isolating layer in a signal processing unit on the semiconductor substrate;

a photodiode in the photosensor unit; and

transistors in the signal processing unit.

19. The CMOS image sensor according to claim 18 , further comprising a contact electrode connected to the second ion implant area, configured to apply a reverse voltage to the second ion implant area.

20. The CMOS image sensor according to claim 18 , wherein the device isolating implant area is formed at boundary between adjacent unit pixels.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041377/0214 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →