IP Library Granted Patent US 9,093,529
Granted Patent B2
US 9,093,529 · App. 12/003,100 · Granted Jul 28, 2015

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

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Quick Facts
Patent No.
US 9,093,529
App. No.
12/003,100
Granted
Jul 28, 2015
Kind
B2
Abstract

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Claims (54)

1. A semiconductor device comprising:

a semiconductor substrate which is a silicon substrate;

a gate insulating film formed on the semiconductor substrate;

a gate electrode formed on the gate insulating film;

a SiGe layer formed in a hole in the semiconductor substrate; and

a sidewall formed on the side of the gate electrode,

wherein a first side surface of the hole is located under the sidewall,

the first side surface includes two crystal planes,

a cross-sectional shape of the first side surface is concave,

each of the two crystal planes of the first side surface is defined by a (111) plane of the silicon substrate, and

the SiGe layer is located under the sidewall and is not located under the gate electrode.

2. The semiconductor device according to claim 1 , wherein a gate width direction of the gate electrode is a [100] direction of the silicon substrate.

3. The semiconductor device according to claim 1 , wherein the entire gate electrode is made of silicide of refractory metal.

4. The semiconductor device according to claim 1 , wherein one of the two crystal planes is connected to the surface of the semiconductor substrate, and another of the two crystal planes is connected to a bottom surface of the hole.

5. The semiconductor device according to claim 1 further comprising:

a channel region in the silicon substrate under the gate electrode; and

a source/drain region located between the (111) plane of the silicon substrate and the channel region.

6. The semiconductor device according to claim 1 , further comprising:

an insulating film formed over the SiGe layer; and

a conductive plug formed in the insulating film and electrically connected to the SiGe layer,

wherein an upper surface of the SiGe layer is located higher than an interface between the silicon substrate and the gate insulating film.

7. The semiconductor device according to claim 6 , further comprising:

a silicide layer formed between the SiGe layer and the conductive plug,

wherein a bottom surface of the silicide layer is located higher than an interface between the silicon substrate and the gate insulating film.

8. The semiconductor device according to claim 7 , wherein the silicide layer includes Pt.

9. The semiconductor device according to claim 1 , further comprising

a silicide layer formed over the SiGe layer,

wherein a second side surface of the hole that faces the first side surface is composed of the silicon substrate.

10. The semiconductor device according to claim 9 , wherein

the second side surface includes two crystal planes, and

each of the two crystal planes of the second side surface is defined by a (111) plane of silicon.

11. The semiconductor device according to claim 10 , wherein the silicide layer includes Pt.

12. A semiconductor device comprising:

a semiconductor substrate which is a silicon substrate;

a gate insulating film formed on the semiconductor substrate;

a gate electrode formed on the gate insulating film;

a sidewall formed on the side of the gate electrode; and

a SiGe layer formed in a hole in the semiconductor substrate,

wherein the hole includes a first side surface that is located under the sidewall and a bottom surface, and

a first angle between the bottom surface of the hole and the first side surface is more gentle than a second angle between a (100) plane of the silicon substrate and a (111) plane of the silicon substrate.

13. The semiconductor device according to claim 12 , wherein

the hole includes a second side surface that faces the first side surface, and

the second side surface is composed of the silicon substrate.

14. The semiconductor device according to claim 13 , wherein a third angle between the bottom surface of the hole and the second side surface is more gentle than the second angle.

15. The semiconductor device according to claim 12 , wherein a gate width direction of the gate electrode is a [100] direction of the silicon substrate.

16. The semiconductor device according to claim 12 , wherein the SiGe layer is located under the sidewall and is not located under the gate electrode.

17. The semiconductor device according to claim 12 , further comprising

an insulating film formed over the SiGe layer; and

a conductive plug formed in the insulating film and electrically connected to the SiGe layer,

wherein an upper surface of the SiGe layer is located higher than an interface between the silicon substrate and the gate insulating film.

18. The semiconductor device according to claim 17 , further comprising:

a silicide layer formed between the SiGe layer and the conductive plug,

wherein a bottom surface of the silicide layer is located higher than an interface between the silicon substrate and the gate insulating film.

19. The semiconductor device according to claim 18 , wherein the silicide layer includes Pt.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →