IP Library Granted Patent US 8,003,301
Granted Patent B2
US 8,003,301 · App. 12/003,887 · Granted Aug 23, 2011

Manufacturing method for semiconductor device

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Quick Facts
Patent No.
US 8,003,301
App. No.
12/003,887
Granted
Aug 23, 2011
Kind
B2
Abstract

A manufacturing method for a semiconductor device having patterns including two adjacent sides forming a corner portion with an external angle and a periodic pattern with a high density arrangement in the same layer is provided with (a) the step of exposing the first divided pattern including a first side which is obtained by dividing the pattern including two sides and the region which corresponds to a first thinned out pattern from which the periodic pattern is thinned out to light through a first mask having a first mask pattern, and (b) the step of exposing the second divided pattern including a second side which is obtained by dividing the pattern including two sides and the region which corresponds to a second thinned out pattern which is obtained by thinning out the periodic pattern to light through a first mask having a second mask pattern.

Claims (48)

1. A manufacturing method for a semiconductor device, wherein

said semiconductor device comprises in the same layer:

an isolated patterned area arranged with low density where intervals between adjacent areas are relatively wide; and

periodically patterned areas arranged with high density where intervals between adjacent areas are relatively narrow, wherein

said isolated patterned area includes first and second sides, the first and second sides are adjacent to each other and form a corner portion of an external angle of less than 180-degrees,

said manufacturing method comprises the steps of:

(a) exposing regions corresponding to a first divided pattern and first thinned out patterns formed by using a first mask having a first mask pattern, the first divided pattern includes said first side and is obtained by dividing said isolated patterned area, and the first thinned out patterns are obtained by thinning out said periodically patterned areas; and

(b) exposing regions corresponding to a second divided pattern and second thinned out patterns formed by using a second mask having a second mask pattern, the second divided pattern includes said second side and is obtained by dividing said isolated patterned area, and the second thinned out patterns are obtained by thinning out said periodically patterned areas,

wherein said first mask pattern and said second mask pattern have a region which overlaps in the vicinity of a divided portion,

wherein the isolated patterned area is an active pattern, a part of the active pattern is formed by the first mask pattern, a part of the active pattern is formed by the second mask pattern, and the region which overlaps in the vicinity of the divided portion is masked in common through exposure to light by using the first and second mask patterns.

2. The manufacturing method for a semiconductor device according to claim 1 , wherein

said semiconductor device further comprises a gate pattern arranged above said isolated patterned area and in proximity to said corner portion, wherein

said isolated patterned area is a patterned active region as the active pattern.

3. The manufacturing method for a semiconductor device according to claim 1 , wherein said steps (a) and (b) comprise the step of transferring said first and second mask patterns to a hard mask.

4. The manufacturing method for a semiconductor device according to claim 1 , wherein said first mask and said second mask are provided by forming separate regions of said first and second mask patterns on the same mask substrate.

5. A manufacturing method for a semiconductor device, wherein

said semiconductor device comprises:

a patterned active region, including first and second sides, the first and second sides are adjacent to each other and form a corner portion of an external angle of less than 180 degrees; and

a patterned gate arranged above said patterned active region and in proximity to said corner portions,

said manufacturing method comprising the steps of:

(a) exposing a region corresponding to a first divided pattern formed by using a first mask having a first mask pattern, the first divided pattern which includes said first side and is obtained by dividing the patterned active region; and

(b) exposing a region corresponding to a second divided pattern formed by using a second mask having a second mask pattern, the second divided pattern which includes said second side and is obtained by dividing the patterned active region,

wherein said first mask pattern and said second mask pattern have a region which overlaps in the vicinity of a divided portion, and

wherein a part of the patterned active pattern is formed by the first mask pattern, a part of the patterned active pattern is formed by the second mask pattern, and the region which overlaps in the vicinity of the divided portion is masked in common through exposure to light by using the first and second mask patterns.

6. The manufacturing method for a semiconductor device according to claim 5 , wherein

said semiconductor device further comprises periodically patterned areas arranged with high density where intervals between adjacent areas are relatively narrow in the same layer as said patterned active region,

said patterned active region is isolated patterned areas arranged with a low density where intervals between adjacent areas are relatively wide,

said step (a) includes the step of exposing regions corresponding to the first divided pattern and first thinned out patterns formed by using the first mask having the first mask pattern, the first divided pattern is obtained by dividing said isolated patterned areas, and the first thinned out patterns are obtained by thinning out said periodically patterned areas, and

said step (b) includes the step of exposing regions corresponding to the second divided pattern and second thinned out patterns formed by using a second mask having a second mask pattern, the second divided pattern is obtained by dividing said isolated patterned areas, and the second thinned out patterns which are obtained by thinning out said periodically patterned areas.

7. A manufacturing method for a semiconductor device, wherein

said semiconductor device comprises:

a patterned active region including first and second sides, the first and second sides are adjacent to each other and form a corner portion of an external angle of less than 180 degrees; and

a patterned gate arranged above said patterned active region and in proximity to said corner portion,

said manufacturing method comprising the steps of:

(a) exposing a region corresponding to a first divided pattern formed by using a first mask having a first mask pattern, the first divided pattern includes said first side and is obtained by dividing the patterned active region; and

(b) exposing a region corresponding to a second divided pattern formed by using a second mask having a second mask pattern, the second divided pattern includes said second side and is obtained by dividing patterned active region, wherein

said first mask pattern and said second mask pattern have a region which overlaps in the vicinity of a divided portion, and

wherein a part of the patterned active pattern is formed by the first mask pattern, a part of the patterned active pattern is formed by the second mask pattern, and the region which overlaps in the vicinity of the divided portion is masked in common through exposure to light by using the first and second mask patterns.

8. A manufacturing method for a semiconductor device, wherein

said semiconductor device comprises in the same layer:

an isolated patterned area where intervals between adjacent areas are first intervals; and

periodically patterned areas where intervals between adjacent areas are smaller than those of said isolated patterned area, wherein

said isolated patterned area includes first and second sides, the first and second sides are adjacent to each other and form a corner portion with an external angle of less than 180 degrees,

said manufacturing method comprises the steps of:

(a) exposing regions corresponding to a first divided pattern and first thinned out patterns formed by using a first mask having a first mask pattern, the first divided pattern includes said first side and is obtained by dividing said isolated patterned area, and the first thinned out patterns are obtained by thinning out said periodically patterned areas; and

(b) exposing regions corresponding to a second divided pattern and second thinned out patterns formed by using a second mask having a second mask pattern, the second divided pattern includes said second side and is obtained by dividing said isolated patterned area, and the second thinned out patterns are obtained by thinning out said periodically patterned areas,

wherein said first mask pattern and said second mask pattern have a region which overlaps in the vicinity of a divided portion, and

wherein the isolated patterned area is an active pattern, a part of the active pattern is formed by the first mask pattern, a part of the active pattern is formed by the second mask pattern, and the region which overlaps in the vicinity of the divided portion is masked in common through exposure to light by using the first and second mask patterns.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Sep 9, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025008/0390 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2008
From: IMAI, AKIRA; SHINOHARA, MASAAKI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 020364/0518 →