Methods for nanopatterning and production of nanostructures
Methods for nanopatterning and methods for production of nanoparticles utilizing such nanopatterning are described herein. In exemplary embodiments, masking nanoparticles are disposed on various substrates and to form a nanopatterned mask. Using various etching and filling techniques, nanoparticles and nanocavities can be formed using the masking nanoparticles and methods described throughout.
1 . A method for generating one or more nanostructures of a charge storage layer, comprising:
(a) disposing one or more masking nanoparticles on a charge storage layer substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming substrate nanostructures at the site of the masking nanoparticles; and
(c) removing the masking nanoparticles.
2 . The method of claim 1 , wherein the disposing is on a metal charge storage layer substrate.
3 . The method of claim 2 , wherein the disposing is on a metal charge storage layer substrate selected from the group consisting of W, WN 2 , TaN, and Iridium.
4 . The method of claim 1 , wherein the disposing comprises spin coating the masking nanoparticles.
5 . The method of claim 4 , wherein spin coating comprises spin coating Pd, Ni, Ru, Co, or Au nanoparticles.
6 . The method of claim 1 , wherein the removing in (b) comprises etching the charge layer substrate material, but not the masking nanoparticles.
7 . The method of claim 6 , wherein the etching comprises anisotropically etching the charge layer substrate material.
8 . The method of claim 7 , wherein the etching comprises reactive ion etching or electron beam etching.
9 . The method of claim 1 , wherein the removing the masking nanoparticles in (c) comprises rinsing the substrate surface with a solution.
10 . The method of claim 1 , wherein the disposing comprises disposing masking nanoparticles that are between about 1-10 nm in diameter, and wherein the nanostructures that are generated are between about 1-10 nm in diameter.
11 . The method of claim 1 , wherein the disposing comprises disposing masking nanoparticles that are between about 1-5 nm in diameter, and wherein the nanostructures that are generated are between about 1-5 nm in diameter.
12 . A method for generating nanoscale cavities in a substrate material, comprising:
(a) disposing a negative photo-resistant layer on a substrate;
(b) disposing one or more masking nanoparticles on the negative photo-resistant layer, wherein the nanoparticles cover at least a portion of the layer;
(c) reacting one or more uncovered portions of the negative photo-resistant layer to form one or more etch masks comprising one or more portions of reacted negative photo-resistant layer and one or more portions of un-reacted negative photo-resistant layer;
(d) removing the masking nanoparticles, thereby revealing the one or more portions of un-reacted negative photo-resistant layer;
(e) removing the un-reacted portions of the photo-resistant layer, thereby revealing one or more exposed substrate sections; and
(f) removing at least a portion of the one or more exposed substrate sections, thereby forming nanoscale cavities in the substrate.
13 - 24 . (canceled)
25 . A method for generating one or more nanostructures, comprising:
(a) forming one or more nanoscale cavities in a substrate material according to the method of claim 12 ;
(b) disposing a filler material in the nanoscale cavities; and
(c) removing excess filler material that is above the plane of the substrate, thereby forming one or more nanostructures in the nanoscale cavities.
26 - 36 . (canceled)
37 . A method for generating one or more nanostructures, comprising:
(a) disposing one or more masking nanoparticles on a substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming substrate pillars at the portion of the substrate covered by the masking nanoparticles, and forming substrate cavities at a portion of the substrate not covered by the masking nanoparticles;
(c) removing the masking nanoparticles;
(d) disposing an insulating layer on the pillars and at least partially in the cavities, wherein a pit is maintained at the site of the cavities; and
(e) disposing a filler material on the insulating layer, wherein the filler material forms nanostructures confined to the pits.
38 - 67 . (canceled)
68 . A nanostructure of a charge storage layer produced by a process comprising:
(a) disposing one or more masking nanoparticles on a charge storage layer substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming substrate nanostructures at sites of the masking nanoparticles; and
(c) removing the masking nanoparticles.
69 . A nanoscale cavity in a substrate material produced by a process comprising:
(a) disposing a negative photo-resistant layer on a substrate;
(b) disposing one or more masking nanoparticles on the negative photo-resistant layer, wherein the nanoparticles cover at least a portion of the layer;
(c) reacting one or more uncovered portions of the negative photo-resistant layer resistant to form one or more etch masks thereby forming one or more portions of reacted negative photo-resistant layer and one or more portions of un-reacted photo-resistant layer;
(d) removing the masking nanoparticles, thereby revealing the one or more portions of un-reacted negative photo-resistant layer;
(e) removing the un-reacted portions of the photo-resistant layer, thereby revealing one or more exposed substrate sections; and
(f) removing at least a portion of the one or more exposed substrate sections, thereby forming nanoscale cavities in the substrate.
70 . A nanostructure produced by a process comprising:
(a) disposing a negative photo-resistant layer on a substrate;
(b) disposing one or more masking nanoparticles on the negative photo-resistant layer, wherein the nanoparticles cover at least a portion of the layer;
(c) reacting one or more uncovered portions of the negative photo-resistant layer resistant to form one or more etch masks thereby forming one or more portions of reacted negative photo-resistant layer and one or more portions of un-reacted photo-resistant layer;
(d) removing the masking nanoparticles, thereby revealing the one or more portions of un-reacted negative photo-resistant layer;
(e) removing the un-reacted portions of the photo-resistant layer, thereby revealing one or more exposed substrate sections;
(f) removing at least a portion of the one or more exposed substrate sections, thereby forming nanoscale cavities in the substrate;
(g) disposing a filler material in the nanoscale cavities; and
(h) removing excess filler material that is above the plane of the substrate, thereby forming one or more nanostructures in the nanoscale cavities.
71 . A nanostructure produced by a process comprising:
(a) disposing one or more masking nanoparticles on a substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming substrate pillars at the portion of the substrate covered by the masking nanoparticles, and forming substrate cavities at a portion of the substrate not covered by the masking nanoparticles;
(c) removing the masking nanoparticles;
(d) disposing an insulating layer on the pillars and at least partially in the cavities, wherein a pit is maintained at the site of the cavities; and
(e) disposing a filler material on the insulating layer, wherein the filler material forms nanostructures confined to the pits.
72 . A plurality of metallic nanostructures, wherein:
the nanostructures comprise diameters between about 1 nanometer and about 10 nanometers;
the nanostructures comprise diameters with size distributions no greater than about 15% of a mean diameter of the nanostructures;
a center-to-center spacing between adjacent nanostructures is between about 1 nanometer and about 10 nanometers; and
a center-to-center spacing between adjacent nanostructures is controlled to comprise a variance of about 10%.
73 . (canceled)
74 . (canceled)
75 . A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between the source region and the drain region;
an insulating layer of electrically insulating material disposed over the channel region;
a floating gate layer of electrically conducting material disposed over the insulating layer;
a layer of electrically insulating material disposed over the floating gate layer; and
a gate electrode overlying the layer of insulating material,
wherein, the floating gate layer comprises a plurality of discrete nanostructures of claim 72 .
76 . A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between the source region and the drain region;
an insulating layer of electrically insulating material disposed over the channel region;
a floating gate layer of electrically conducting material disposed over the insulating layer;
a layer of electrically insulating material disposed over the floating gate layer; and
a gate electrode overlying the layer of insulating material,
wherein the floating gate layer comprises a plurality of discrete electrically conducting nanostructures prepared by a process comprising:
(a) disposing one or more masking nanoparticles on an electrically conducting substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming electrically conducting substrate nanostructures at sites of the masking nanoparticles; and
(c) removing the masking nanoparticles.
77 . A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between the source region and the drain region;
an insulating layer of electrically insulating material disposed over the channel region;
a floating gate layer of electrically conducting material disposed in the insulating layer;
a layer of electrically insulating material disposed over the floating gate layer; and
a gate electrode overlying the layer of insulating material,
wherein, the floating gate layer comprises a plurality of discrete electrically conducting nanostructures prepared by a process comprising:
(a) disposing a negative photo-resistant layer on the insulating layer;
(b) disposing one or more masking nanoparticles on the negative photo-resistant layer, wherein the nanoparticles cover at least a portion of the negative photo-resistant layer;
(c) reacting one or more uncovered portions of the negative photo-resistant layer resistant to form one or more etch masks comprising one or more portions of reacted negative photo-resistant layer and one or more portions of un-reacted photo-resistant layer;
(d) removing the masking nanoparticles, thereby revealing the one or more portions of un-reacted negative photo-resistant layer;
(e) removing the un-reacted portions of the photo-resistant layer, thereby revealing one or more exposed insulating layer sections; and
(f) removing at least a portion of the one or more exposed insulating layer sections, thereby forming nanoscale cavities in the insulating layer;
(g) disposing an electrically conducting filler material in the nanoscale cavities; and
(h) removing excess filler material that is above the plane of the insulating layer, thereby forming one or more electrically conducting nanostructures in the nanoscale cavities.
78 . A field effect transistor, comprising:
a source region and a drain region formed in a semiconductor material;
a channel region disposed between the source region and the drain region;
an insulating layer of electrically insulating material disposed over the channel region;
a floating gate layer of electrically conducting material disposed in the insulating layer;
a layer of electrically insulating material disposed over the floating gate layer; and
a gate electrode overlying the layer of insulating material,
wherein, the floating gate layer comprises a plurality of discrete electrically conducting nanostructures prepared by a process comprising:
(a) disposing one or more masking nanoparticles on a substrate, wherein the nanoparticles cover at least a portion of the substrate;
(b) removing uncovered substrate material, thereby forming substrate pillars at the portion of the substrate covered by the masking nanoparticles, and forming substrate cavities at a portion of the substrate not covered by the masking nanoparticles;
(c) removing the masking nanoparticles;
(d) disposing an insulating layer of electrically insulating material on the pillars and at least partially in the cavities, wherein a pit is maintained at the site of the cavities; and
(e) disposing an electrically conducting filler material on the insulating layer, wherein the filler material forms electrically conducting nanostructures confined to the pits.
79 . A method for generating nanoscale cavities in a substrate material, comprising:
(a) providing a support structure;
(b) disposing one or more masking nanoparticles on the support structure;
(c) disposing a substrate material on the masking nanoparticles and the support structure, thereby covering the masking nanoparticles;
(d) removing at least a portion of the substrate material, thereby revealing at least a portion of the masking nanoparticles;
(e) removing the masking nanoparticles, thereby forming nanoscale cavities in the substrate material.
80 - 103 . (canceled)
104 . A method for generating a nanoscale phase change layer, comprising:
(a) forming one or more nanoscale cavities in a substrate material according to the method of claim 79 ; and
(b) disposing a phase change material in at least the nanoscale cavities.
105 . The method of claim 104 , wherein the disposing comprises chemical vapor deposition of the nanoscale phase change layer.
106 - 108 . (canceled)
109 . A method for generating a phase change memory (PCM) cell, comprising:
(a) forming one or more nanoscale cavities in a substrate material according to the method of claim 79 ;
(b) disposing a phase change material in at least the nanoscale cavities; and
(c) electrically connecting the phase change material to an electrical contact, thereby forming a PCM cell.
110 - 119 . (canceled)
120 . A method for generating one or more nanowires, comprising:
(a) providing a substrate material;
(b) disposing one or more masking nanoparticles on the substrate, wherein the nanoparticles cover at least a portion of the substrate;
(c) removing uncovered substrate material, thereby forming substrate nanowires at the site of the masking nanoparticles, wherein the nanowires are greater than 20 nm in length; and
(d) removing the masking nanoparticles.
121 - 130 . (canceled)
131 . A method for generating one or more transistor switches, comprising:
(a) providing a substrate material;
(b) disposing one or more masking nanoparticles on the substrate, wherein the nanoparticles cover at least a portion of the substrate;
(c) removing uncovered substrate material, thereby forming substrate nanowires at the site of the masking nanoparticles;
(d) removing the masking nanoparticles;
(e) growing a first oxide layer on the substrate and substrate nanowires;
(f) disposing a filler material;
(g) removing a portion of the filler material, whereby a cavity is formed in the filler material between substrate nanowires;
(h) disposing a second oxide layer; and
(i) removing the first and the second oxide layer, whereby a portion of the substrate nanowires are exposed, and whereby the filler material is not exposed.
132 - 161 . (canceled)
162 . A method for generating an array of electrically connected phase change memory (PCM) cells, comprising:
(a) forming two or more transistor switches according to the method of claim 131 ;
(b) generating masked and unmasked alternating lines, wherein the lines comprise substrate nanowires and filler material;
(c) removing unmasked alternating lines, thereby forming troughs between masked lines;
(d) disposing an insulating material in the troughs;
(e) exposing a portion of the substrate nanowires;
(f) electrically connecting the filler material in each line;
(g) disposing a phase change material layer; and
(h) electrically connecting one or more substrate nanowires in each line.
163 - 170 . (canceled)
171 . A transistor switch, comprising:
(a) one or more transistor nanowires;
(b) an electrically conductive gate material surrounding the nanowires;
(c) an insulating material separating the nanowires from the electrically conductive gate material;
(d) an electrical connection to the gate material; and
(e) an electrical connection to the nanowires.
172 - 175 . (canceled)
176 . A phase change memory (PCM) cell, comprising:
(a) one or more transistor nanowires;
(b) an electrically conductive gate material surrounding the nanowires;
(c) a phase change material layer contacting at least a portion of at least one nanowire;
(d) an insulating material separating the nanowires from the electrically conductive gate material, and separating the electrically conductive gate material from the phase change material layer; and
(e) an electrical connection to the phase change material layer.
177 - 185 . (canceled)