IP Library Assignment 038809/0672
Patent Assignment
Reel/Frame 038809/0672

CHANGE OF NAME

Recorded: 2016-05-25 Received: 2016-05-25 Pages: 28
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications (100)
Open Erase Block Read Automation
App. No. 62/147,546
Mapping Logical Groups of Data to Physical Locations in Memory
App. No. 62/144,847
MEASURING MEMORY WEAR AND DATA RETENTION INDIVIDUALLY BASED ON CELL VOLTAGE DISTRIBUTIONS
App. No. 62/095,608
DECODING TECHNIQUES FOR LOW-DENSITY PARITY CHECK CODES
App. No. 14/321,069
Low-Test Memory Stack for Non-Volatile Storage
App. No. 62/012,918
3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter
App. No. 14/279,405
Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device
App. No. 14/278,672
Methods and Systems for Efficient Non-Isolated Transactions
App. No. 61/973,215
Efficient Cache Utilization in a Tiered Data Structure
App. No. 61/973,170
GROUPING STORAGE PORTS BASED ON DISTANCE
App. No. 61/951,944
NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING
App. No. 14/201,899
SYSTEMS AND METHODS FOR STORAGE VIRTUALIZATION
App. No. 61/946,708
NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL
App. No. 14/183,797
ON DIE BUFFERED NON-VOLATILE MEMORY MANAGEMENT
App. No. 61/925,549
METHOD AND APPARATUS FOR STORING DATA IN NON-VOLATILE MEMORY
App. No. 14/144,061
Storage Module and Method for Re-Enabling Preloading of Data in the Storage Module
App. No. 14/137,367
DECODING TECHNIQUES FOR A DATA STORAGE DEVICE
App. No. 14/107,973
Simulated Power Failure and Data Hardening Circuitry Architecture
App. No. 61/903,895
Method for Versatile Content Control with Partitioning
App. No. 14/067,574
Semiconductor Device Manufacturing Line
App. No. 14/032,041
FET LOW CURRENT 3D ReRAM NON-VOLATILE STORAGE
App. No. 14/025,420
Nonvolatile Memory System Compression
App. No. 14/016,954
Write Amplification Reduction Through Reliable Writes During Garbage Collection
App. No. 61/870,171
CONTROLLER BASED MEMORY EVALUATION
App. No. 13/943,516
Efficient Post Write Read in Three Dimensional Nonvolatile Memory
App. No. 13/929,368
APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY
App. No. 13/911,294
METHOD AND SYSTEM FOR STORAGE ADDRESS RE-MAPPING FOR A MULTI-BANK MEMORY DEVICE
App. No. 13/897,126
STORAGE CONTROL SYSTEM WITH FLASH CONFIGURATION AND METHOD OF OPERATION THEREOF
App. No. 13/867,017
STORAGE CONTROL SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF
App. No. 61/809,253
OBJECT-BASED MEMORY STORAGE
App. No. 13/835,109
DATA TAG SHARING FROM HOST TO STORAGE SYSTEMS
App. No. 13/834,282
METHOD AND SYSTEM FOR RAM CACHE COALESCING
App. No. 13/838,582
Duty-Cycle Dependent Slope Compensation for a Current Mode Switching Regulator
App. No. 13/840,035
Remapping Blocks in a Storage Device
App. No. 13/831,374
TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
App. No. 13/794,182
Flash Memory Interface Using Split Bus Configuration
App. No. 13/793,609
METHODS AND APPARATUS FOR METAL OXIDE REVERSIBLE RESISTANCE-SWITCHING MEMORY DEVICES
App. No. 13/792,100
MIIIM DIODE HAVING LANTHANUM OXIDE
App. No. 13/787,505
DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME
App. No. 13/780,089
Apparatus, System, and Method for Storing Metadata
App. No. 13/776,389
USAGE OF CACHE AND WRITE TRANSACTION INFORMATION IN A STORAGE DEVICE
App. No. 13/775,896
MEMORY ACCESS SYSTEM AND METHOD OF ACCESS THEREOF
App. No. 61/767,234
NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING
App. No. 13/743,502
BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS
App. No. 13/740,766
Compressing Data from Multiple Reads for Error Control Management in Memory Systems
App. No. 61/746,551
Method and Apparatus for DMA Transfer with Synchronization Optimization
App. No. 61/731,331
USAGE OF CACHE AND WRITE TRANSACTION INFORMATION IN A STORAGE DEVICE
App. No. 61/727,479
METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE
App. No. 13/678,894
Self-Aligned Planar Flash Memory And Methods Of Fabrication
App. No. 13/646,500
Method and Host Device for Assessing Execution of Trim Commands
App. No. 13/524,924
Method and Host Device for Dispatching a Packed Command
App. No. 61/654,031
APPARATUS, SYSTEM, AND METHOD FOR EFFICIENT MAPPING OF VIRTUAL AND PHYSICAL ADDRESSES
App. No. 13/480,791
Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory
App. No. 13/479,649
Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions
App. No. 13/468,720
RESISTANCE-SWITCHING MEMORY CELLS HAVING REDUCED METAL MIGRATION AND LOW CURRENT OPERATION AND METHODS OF FORMING THE SAME
App. No. 13/465,263
SELECTIVELY USING LOCAL NON-VOLATILE STORAGE IN CONJUNCTION WITH TRANSMISSION OF CONTENT
App. No. 13/449,894
HOUSING AND CLIP ASSEMBLY FOR PORTABLE ELECTRONICS DEVICE
App. No. 13/439,904
Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques
App. No. 13/433,584
Memory Card
App. No. 13/434,438
MULTIPLE PRE-DRIVER LOGIC FOR IO HIGH SPEED INTERFACES
App. No. 13/408,638
Storage Management and Acceleration of Storage Media in Clusters
App. No. 13/402,833
MEMORY SYSTEM WITH TIERED QUEUING AND METHOD OF OPERATION THEREOF
App. No. 13/368,224
Host Device and Method for Partitioning Attributes in a Storage Device
App. No. 13/341,649
LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE
App. No. 61/582,017
AUXILIARY CARD INITIALIZATION ROUTINE
App. No. 13/336,223
Systems and Methods for Managing Parallel Access to Multiple Storage Systems
App. No. 13/335,217
APPARATUS, SYSTEM, AND METHOD FOR PERSISTENT DATA MANAGEMENT ON A NON-VOLATILE STORAGE MEDIA
App. No. 13/330,554
Optical Network for Cluster Computing
App. No. 13/329,252
Storage Device and Method for Super-Distribution of Content Protected with a Localized Content Encyrption Key
App. No. 13/328,843
Non-Volatile Storage Systems with Go To Sleep Adaption
App. No. 13/323,612
ANTIFUSE-BASED MEMORY CELLS HAVING MULTIPLE MEMORY STATES AND METHODS OF FORMING THE SAME
App. No. 13/314,580
SYSTEM AND METHOD OF PROTECTING METADATA FROM NAND FLASH FAILURES
App. No. 13/286,012
METHODS AND APPARATUS FOR INCLUDING AN AIR GAP IN CARBON-BASED MEMORY DEVICES
App. No. 13/241,098
APPARATUS, SYSTEM, AND METHOD FOR REFERENCING DATA BLOCK USAGE INFORMATION BY WAY OF AN INTERFACE
App. No. 13/227,088
STORAGE CONTROL SYSTEM WITH WRITE AMPLIFICATION CONTROL MECHANISM AND METHOD OF OPERATION THEREOF
App. No. 61/530,918
METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE
App. No. 13/215,836
METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICES
App. No. 13/204,772
Apparatus, System, and Method for Storing Data on a Solid-State Storage Device
App. No. 13/174,449
APPARATUS, SYSTEM, AND METHOD FOR PROVIDING ERROR CORRECTION
App. No. 13/161,211
CACHE MANAGEMENT AND ACCELERATION OF STORAGE MEDIA
App. No. 13/153,117
Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof
App. No. 13/151,217
Apparatus, System, and Method for Managing Data From a Requesting Device with an Empty Data Token Directive
App. No. 13/118,237
BLOCK WRITE HANDLING AFTER CORRUPTION
App. No. 13/109,709
WRITE OPERATIONS IN A FLASH MEMORY-BASED OBJECT STORE
App. No. 13/084,432
PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT
App. No. 13/072,130
PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT
App. No. 61/450,528
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 13/027,113
NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF
App. No. 13/020,054
APPARATUS, SYSTEM, AND METHOD FOR DESTAGING CACHED DATA
App. No. 61/435,192
MANUAL SUSPEND AND RESUME FOR NON-VOLATILE MEMORY
App. No. 12/978,001
Auxiliary Interface for Non-Volatile Memory System
App. No. 12/969,167
REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING
App. No. 12/962,902
STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING
App. No. 12/952,944
BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAME
App. No. 12/904,770
HIGH VOLTAGE SWITCH SUITABLE FOR USE IN FLASH MEMORY
App. No. 12/895,476
SEMICONDUCTOR STRUCTURES
App. No. 12/872,468
METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY
App. No. 12/856,392
FLASH BLADE SYSTEM ARCHITECTURE AND METHOD
App. No. 12/853,953
MEMORY ARRAYS INCLUDING MEMORY LEVELS THAT SHARE CONDUCTORS, AND METHODS OF FORMING SUCH MEMORY ARRAYS
App. No. 12/844,037
Audio Visual Player Apparatus and System and Method of Content Distribution Using the Same
App. No. 12/834,515