BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS
In a first aspect, a metal-insulator-metal (“MIM”) stack is provided that includes a first conductive layer, a resistivity-switching layer having a metal oxide layer formed above the first conductive layer, a material layer between the first conductive layer and the resistivity-switching layer, and a second conductive layer above the resistivity-switching layer. The first conductive layer includes a multi-layer metal-silicide stack, and the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
1 . A metal-insulator-metal stack comprising:
a first conductive layer comprising a multi-layer metal-silicide stack;
a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer;
a material layer disposed between the first conductive layer and the resistivity-switching layer, wherein the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV; and
a second conductive layer formed above the resistivity-switching layer.
2 . The metal-insulator-metal stack of claim 1 , wherein the multi-layer metal-silicide stack comprises:
a first metal-silicide layer comprising one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide; and
a second metal-silicide layer comprises a different one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide.
3 . The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.
4 . The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.
5 . The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.
6 . The metal-insulator-metal stack of claim 1 , wherein the first conductive layer has a thickness of about 2-100 nanometers.
7 . The metal-insulator-metal stack of claim 1 , wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .
8 . The metal-insulator-metal stack of claim 1 , wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.
9 . The metal-insulator-metal stack of claim 1 , wherein the material layer comprises a metal, a metal nitride or a metal oxide.
10 . The metal-insulator-metal stack of claim 1 , wherein the material layer comprises at least one of aluminum, aluminum nitride, lanthanum, lanthanum nitride, molybdenum, molybdenum nitride, tantalum, tantalum nitride, chromium, chromium nitride, hafnium, hafnium nitride, niobium, niobium nitride, vanadium, vanadium nitride, zirconium or zirconium nitride.
11 . A memory cell comprising:
the metal-insulator-metal stack of claim 1 ; and
a steering element coupled to the metal-insulator-metal stack.
12 . The memory cell of claim 11 , wherein the steering element comprises a vertical polysilicon diode.
13 . A method of forming a metal-insulator-metal stack comprising:
forming a first conductive layer comprising a multi-layer metal-silicide stack;
forming a resistivity-switching layer comprising a metal oxide layer above the first conductive layer;
forming a material layer between the first conductive layer and the resistivity-switching layer, wherein the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV; and
forming a second conductive layer above the resistivity-switching layer.
14 . The method of claim 13 , wherein the multi-layer metal-silicide stack comprises:
a first metal-silicide layer comprising one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide; and
a second metal-silicide layer comprises a different one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide.
15 . The method of claim 14 , wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.
16 . The method of claim 14 , wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.
17 . The method of claim 14 , wherein the first metal-silicide layer comprises titanium silicide and the second metal-silicide layer comprises tungsten silicide.
18 . The method of claim 14 , wherein the first conductive layer has a thickness of about 2-100 nanometers.
19 . The method of claim 13 , wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .
20 . The method of claim 13 , wherein the material layer comprises a metal, a metal nitride, or a metal oxide.
21 . A memory cell formed using the method of claim 13 .