MEMORY ARRAYS INCLUDING MEMORY LEVELS THAT SHARE CONDUCTORS, AND METHODS OF FORMING SUCH MEMORY ARRAYS

1 . A memory array comprising:

a first memory level comprising:

a first diode; and

a first resistivity-switching material layer coupled in series with the first diode;

a second memory level above the first memory level, the second memory level comprising:

a second diode; and

a second resistivity-switching material layer coupled in series with the second diode; and

a conductor shared between the first and second memory levels,

wherein the first and second resistivity-switching material layers each comprise one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y .

2 . The memory array of claim 1 , wherein the first and second resistivity-switching material layers each have a thickness between about 5 angstroms and about 100 angstroms.

3 . The memory array of claim 1 , wherein the first and second resistivity-switching material layers each comprise HfO 2 or Al 2 O 3 .

4 . The memory array of claim 1 , wherein the first and second resistivity-switching material layers are formed by a deposition process.

5 . The memory array of claim 1 , wherein the first and second resistivity-switching material layers are formed by atomic layer deposition.

6 . The memory array of claim 1 , wherein the first and second diodes comprise p-i-n diodes.

7 . The memory array of claim 1 , wherein the first diode comprises a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region.

8 . The memory array of claim 1 , wherein the second diode comprises a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region

9 . The memory array of claim 1 , wherein the first and second diodes comprise vertical polysilicon diodes.

10 . A memory array comprising:

a first memory level comprising:

a first conductor;

a first diode formed above the first conductor;

a first resistivity-switching material layer formed above the first conductor; and

a second conductor formed above the first diode and the first resistivity-switching material; and

a second memory level comprising:

a second diode formed above the second conductor;

a second resistivity-switching material layer formed above the second conductor; and

a third conductor formed above the second diode and the second resistivity-switching material,

wherein the first memory level and the second memory level share the second conductor, and

wherein the first and second resistivity-switching material layers each comprise one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y .

11 . The memory array of claim 10 , wherein the first and second resistivity-switching material layers each have a thickness between about 5 angstroms and about 100 angstroms.

12 . The memory array of claim 10 , wherein the first and second resistivity-switching material layers each comprise HfO 2 or Al 2 O 3 .

13 . The memory array of claim 10 , wherein the first and second resistivity-switching material layers are formed by a deposition process.

14 . The memory array of claim 10 , wherein the first and second resistivity-switching material layers are formed by atomic layer deposition.

15 . The memory array of claim 10 , wherein the first and second diodes comprise p-i-n diodes.

16 . The memory array of claim 10 , wherein the first diode comprises a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region.

17 . The memory array of claim 10 , wherein the second diode comprises a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region

18 . The memory array of claim 10 , wherein the first and second diodes comprise vertical polysilicon diodes.

19 . A method of forming a memory array, the method comprising:

forming a first memory level by:

forming a first diode; and

forming a first resistivity-switching material layer coupled in series with the first diode;

forming a second memory level above the first memory level by:

forming a second diode; and

forming a second resistivity-switching material layer coupled in series with the second diode; and

forming a conductor shared between the first and second memory levels,

wherein the first and second resistivity-switching material layers each comprise one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y, Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y .

20 . The method of claim 19 , wherein the first and second resistivity-switching material layers each have a thickness between about 5 angstroms and about 100 angstroms.

21 . The method of claim 19 , wherein the first and second resistivity-switching material layers each comprise HfO 2 or Al 2 O 3 .

22 . The method of claim 19 , wherein forming the first and second resistance switching material layers comprises forming the resistivity-switching material layer by a deposition process.

23 . The method of claim 22 , wherein the deposition process comprises an atomic layer deposition process.

24 . The method of claim 19 , wherein the first and second diodes comprise p-i-n diodes.

25 . The method of claim 19 , wherein the first diode comprises a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region.

26 . The method of claim 19 , wherein the second diode comprises a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region

27 . The method of claim 12 , wherein the first and second diodes comprise vertical polysilicon diodes.