IP Library Patent Application 13838582
Patent Application
App. No. 13/838,582

METHOD AND SYSTEM FOR RAM CACHE COALESCING

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Quick Facts
Patent No.
US None
App. No.
13/838,582
Abstract

A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.

Claims (42)

1 . A method of storing data received from a host system, the method comprising:

in a memory device having a non-volatile memory, a volatile memory and a controller in communication with the non-volatile memory and volatile memory, the controller:

receiving data fragments from the host system, each data fragment comprising an amount of data less than a physical page size managed in the non-volatile memory;

storing the data fragments in the volatile memory as they are received;

upon receiving a predetermined number of the data fragments, aggregating the predetermined number of data fragments into a single write command having a second amount of data equal to the physical page size managed in the flash memory; and

writing the second amount of data in the single write command to the non-volatile memory.

2 . The method of claim 1 , further comprising:

if a predetermined amount of time elapses prior to receiving the predetermined number of data fragments:

aggregating data fragments currently stored in the volatile memory into an abbreviated single write command having less than the predetermined number of data fragments; and

writing the abbreviated single write command to the non-volatile memory.

3 . The method of claim 1 , wherein:

the non-volatile memory comprises a binary cache and a long term memory;

the physical page size managed in the flash memory comprises a physical page size of data managed in the binary cache; and

writing the data in the single write command to the non-volatile comprises writing the data in the single write command to the binary cache.

4 . The method of claim 1 , further comprising generating an aggregated index entry identifying a respective location in the non-volatile memory for each of the aggregated data fragments in the single write command.

5 . The method of claim 4 , wherein generating the aggregated index entry comprises aggregating pointer information for each aggregated data fragment into a single entry.

6 . The method of claim 4 , wherein the second amount of data in the single write command comprises a sum of a size of each aggregated data fragment and a size of the aggregated index entry for the aggregated data fragments.

7 . The method of claim 6 , wherein each data fragment has a same size.

8 . A mass storage memory system, comprising:

an interface adapted to receive data from a host system;

a volatile memory;

a non-volatile memory; and

a controller in communication with the interface, volatile memory and the non-volatile memory, wherein the controller is configured to:

receive data fragments from the host system, each data fragment comprising an amount of data less than a physical page size managed in the non-volatile memory;

store the data fragments in the volatile memory as they are received;

upon receiving a predetermined number of the data fragments, aggregate the predetermined number of data fragments into a single write command having a second amount of data equal to the physical page size managed in the flash memory; and

write the second amount of data in the single write command to the non-volatile memory.

9 . The mass storage memory system claim 8 , wherein the controller is further configured to:

if a predetermined amount of time elapses prior to receiving the predetermined number of data fragments:

aggregate data fragments currently stored in the volatile memory into an abbreviated single write command having less than the predetermined number of data fragments; and

write the abbreviated single write command to the non-volatile memory.

10 . The mass storage memory system of claim 8 , wherein:

the non-volatile memory comprises a binary cache and a long term memory;

the physical page size managed in the flash memory comprises a physical page size of data managed in the binary cache; and

the controller is configured to write the data in the single write command to the binary cache.

11 . The mass storage memory system of claim 8 , wherein the controller is further configured to generate an aggregated index entry identifying a respective location in the non-volatile memory for each of the data fragments aggregated in the single write command.

12 . The mass storage memory system of claim 11 , wherein to generate the aggregated index entry, the controller is further configured to aggregate pointer information for each aggregated data fragment into a single entry.

13 . The mass storage memory system of claim 11 , wherein the second amount of data in the single write command comprises a sum of a size of each aggregated data fragment and a size of the aggregated index entry for the aggregated data fragments.

14 . The mass storage memory system of claim 13 , wherein each data fragment has a same size.

15 . The mass storage memory system of claim 8 , wherein the volatile memory comprises random access memory RAM sized to store at least the predetermined number of data fragments.

16 . The mass storage memory system of claim 15 , wherein the RAM is internal to the controller.

17 . The mass storage memory device of claim 15 , wherein a size of each of the data fragments is identical and the physical page size managed in the non-volatile memory comprises a whole number multiple of the size of each of the data fragments.

Assignments (2)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038809/0672 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2013
From: BUNDUKIN, MARIELLE; NG, KING YING; SPROUSE, STEVEN T.; WU, WILLIAM; GOROBETS, SERGEY ANATOLIEVICH; PARKER, LIAM; BENNETT, ALAN DAVID
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 031269/0152 →