Clock pulse generating circuit
A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator.
1. A clock pulse generating circuit comprising:
a pulse generator configured to vary a first pulse width of a rising clock signal and a second pulse width of a falling clock signal;
a clock regulator configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator; and
a pre-driver configured to output data driving signals according to output signals of the clock regulator,
wherein the clock regulator comprises:
a first regulation part configured to regulate a first clock signal and a second clock signal output from the pulse generator by using an SR latch circuit; and
a second regulation part configured to regulate output signals of the first regulation part by using an SR latch circuit.
2. The clock pulse generating circuit of claim 1 , wherein the pulse generator comprises:
a first variation part configured to vary said first pulse width of the rising clock signal; and
a second variation part configured to vary said second pulse width of the falling clock signal.
3. The clock pulse generating circuit of claim 2 , wherein the first variation part comprises:
a first delay unit configured to delay the rising clock signal by a predetermined time; and
a first logic unit configured to perform a logic operation on the rising clock signal and an output signal of the first delay unit.
4. The clock pulse generating circuit of claim 2 , wherein the second variation part comprises:
a second delay unit configured to delay the falling clock signal by a predetermined time; and
a second logic unit configured to perform a logic operation on the falling clock signal and an output signal of the second delay unit.
5. The clock pulse generating circuit of claim 1 , wherein the first clock signal is generated by varying said first pulse width of the rising clock signal, and the second clock signal is generated by varying said second pulse width of the falling clock signal.
6. The clock pulse generating circuit of claim 1 , wherein the first regulation part comprises:
a first logic unit configured to perform a logic operation on the first clock signal; and
a second logic unit configured to perform a logic operation on the second clock signal, an output signal of the first logic unit being input into the second logic unit, an output signal of the second logic unit being input into the first logic unit.
7. The clock pulse generating circuit of claim 6 , wherein the second regulation part comprises:
a third logic unit configured to perform a logic operation on an output signal of the first logic unit; and
a fourth logic unit configured to perform a logic operation on an output signal of the second logic unit, an output signal of the third logic unit being input into the fourth logic unit, an output signal of the fourth logic unit being input into the third logic unit.
8. The clock pulse generating circuit of claim 1 , wherein the pre-driver comprises an inverter unit configured to invert the output signals of the clock regulator.
9. The clock pulse generating circuit of claim 8 , wherein the pre-driver further comprises a buffer unit configured to buffer the output signals of the clock regulator.