Read and volatile NV standby disturb
View Patent ↗A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.
1. A method of operating a nonvolatile memory circuit, the method comprising:
asserting a positive gate bias on an isolation transistor between a voltage-current source node and a nonvolatile bit charge storage transistor during nonvolatile STANDBY.
2. The method of claim 1 , further comprising:
asserting the gate bias on the isolation transistor during one or more of ERASE, STORE, and RECALL operations.
3. The method of claim 1 , further comprising:
maintaining the voltage-current source node unasserted during STANDBY, asserting the source node at or near the beginning of a RECALL operation, and unasserting the voltage-current source node at or near a time when the nonvolatile bit is sensed.
4. The method of claim 1 , wherein the memory circuit comprises:
the charge storage transistor is a SONOS transistor.
5. The method of claim 1 , wherein the memory circuit comprises: the isolation transistor arranged between the voltage-current source node and the charge storage transistor; and
a second isolation transistor arranged between the charge storage transistor and the recall sink node.
6. A memory circuit comprising:
at least one charge storage transistor for storage of a charge representing a nonvolatile memory bit; and
electrical circuitry comprising logic to assert a positive gate bias on an isolation transistor between the voltage-current source node and the charge storage transistor during nonvolatile STANDBY.
7. The memory circuit of claim 6 , further comprising:
electrical circuitry comprising logic to assert the gate bias on the isolation transistor during one or more of ERASE, STORE, and RECALL operations.
8. The memory circuit of claim 6 , further comprising:
electrical circuitry comprising logic to maintain the voltage-current source node unasserted during STANDBY, assert the source node at or near the beginning of a RECALL operation, and unassert the voltage-current source node at or near a time when the nonvolatile bit is sensed.
9. The memory circuit of claim 6 , further comprising:
the charge storage transistor is a SONOS transistor.
10. The memory circuit of claim 6 , further comprising:
the isolation transistor arranged between the voltage-current source node and the charge storage transistor; and
a second isolation transistor arranged between the charge storage transistor and the recall sink node.
11. A memory circuit comprising:
at least one nonvolatile charge storage transistor for storage of a charge representing a nonvolatile memory bit;
at least one volatile storage cell associated with the nonvolatile charge storage transistor, and
electrical circuitry comprising logic to assert a positive gate bias on an isolation transistor between the voltage-current source node and the nonvolatile charge storage transistor during nonvolatile STANDBY.
12. The memory circuit of claim 11 , further comprising:
electrical circuitry comprising logic to assert the gate bias on the isolation transistor during one or more of ERASE, STORE, and RECALL operations.
13. The memory circuit of claim 11 , further comprising:
electrical circuitry comprising logic to maintain the voltage-current source node unasserted during STANDBY, assert the source node at or near the beginning of a RECALL operation, and unassert the voltage-current source node at or near a time when the nonvolatile bit is sensed.
14. The memory circuit of claim 11 , further comprising:
the nonvolatile charge storage transistor is a SONOS transistor.
15. The memory circuit of claim 11 , further comprising:
the isolation transistor arranged between the voltage-current source node and the nonvolatile charge storage transistor, and
a second isolation transistor arranged between the nonvolatile charge storage transistor and the recall sink node.