NAND power fail recovery
View Patent ↗Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.
1. A method to recover the state of data stored in NAND memory after power failure in an electronic device, comprising:
detecting, during power failure recovery, a page state associated with a NAND page;
determining whether to include the NAND page in an L2P rebuild operation based at least in part on the page state associated with the NAND page; and
updating the L2P table with data from the NAND page, by performing operations comprising:
determining a number of ECC errors or corrections associated with a new page address and the current page address; and
updating the L2P table when the number of ECC errors or corrections associated with the new page address is less than the number of ECC errors or corrections associated with the current page address.
2. The method of claim 1 , wherein detecting a page state comprises detecting whether the NAND page is in a blank state.
3. The method of claim 1 , wherein detecting a page state comprises determining whether the NAND page is free of ECC errors.
4. The method of claim 1 , wherein detecting a page state comprises determining whether a number of ECC corrections associated with a page exceeds a threshold.
5. The method of claim 1 , wherein updating the L2P table comprises:
determining a number of ECC errors or corrections associated with a new page address and the current page address; and
bypassing an update on the L2P table when the number of ECC errors or corrections associated with the new page address is greater than the number of ECC errors or corrections associated with the current page address.
6. A system to recover the state of data stored in NAND memory after power failure in an electronic device, comprising logic circuitry to:
detect, during power failure recovery, a page state associated with a NAND page;
determine whether to include the NAND page in an L2P rebuild operation based at least in part on the page state associated with the page;
determine a number of ECC errors or corrections associated with a new page address and the current page address; and
update the L2P table with data from the NAND page when the number of ECC errors or corrections associated with the new page address is less than the number of ECC errors or corrections associated with the current page address.
7. The system of claim 6 , further comprising logic circuitry to detect whether the NAND page is in a blank state.
8. The system of claim 6 , further comprising logic circuitry to determine whether the NAND page is free of ECC errors.
9. The system of claim 6 , further comprising logic circuitry to determine whether a number of ECC errors associated with a page exceeds a threshold.
10. The system of claim 6 , further comprising logic circuitry to:
determine a number of ECC errors or corrections associated with a new page address and the current page address; and
bypass an update on the L2P table when the number of ECC errors or corrections associated with the new page address is greater than the number of ECC errors or corrections associated with the current page address.
11. A system to recover the state of data stored in NAND memory after power failure in an electronic device, comprising logic instructions stored on a tangible computer readable medium which, when executed by a processor, configure the processor to:
detect, during power failure recovery, a page state associated with a NAND page;
determine whether to include the NAND page in an L2P rebuild operation based at least in part on the page state associated with the page;
determine a number of ECC errors or corrections associated with a new page address and the current page address; and
update the L2P table with data from the NAND page when the number of ECC errors or corrections associated with the new page address is less than the number of ECC errors or corrections associated with the current page address.
12. The system of claim 11 , further comprising logic instructions stored on a tangible computer readable medium which, when executed by a processor, configure the processor to detect whether the NAND page is in a blank state.
13. The system of claim 11 , further comprising logic instructions stored on a tangible computer readable medium which, when executed by a processor, configure the processor to determine whether the NAND page is free of ECC errors.
14. The system of claim 6 , further comprising logic instructions stored on a tangible computer readable medium which, when executed by a processor, configure the processor to determine whether a number of ECC errors associated with a page exceeds a threshold.
15. The system of claim 6 , further comprising logic instructions stored on a tangible computer readable medium which, when executed by a processor, configure the processor to:
determine a number of ECC errors or corrections associated with a new page address and the current page address; and
bypass an update on the L2P table when the number of ECC errors or corrections associated with the new page address is greater than the number of ECC errors or corrections associated with the current page address.