Method for fabricating circuit board structure with capacitors embedded therein

1. A method for fabricating a circuit board structure with capacitors embedded therein, comprising:

providing a first core layer comprising a dielectric layer having two opposite surfaces, first metal layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the first metal layer at the same side;

providing a second core layer and a third core layer individually comprising a dielectric layer having a first surface and a second surface opposite to the first surface, a first metal layer disposed on the first surface of the dielectric layer, and at least one capacitor embedded on the inside of the first surface with the first metal layer disposed on the outside thereof of the dielectric layer and electrically connecting with the first metal layer;

patterning the two first metal layers of the first core layer to form circuit layers;

laminating the two surfaces of the first core layer with the second surfaces of the dielectric layers of the second core layer and the third core layer, respectively, to form a core structure, wherein the second surfaces of the dielectric layers have no capacitors and metal layers respectively on the inside and the outside thereof; and

patterning the first metal layers of the second core layer and the third core layer to form circuit layers;

wherein each of the capacitors comprises: a first electrode plate disposed on the outside of one surface of the dielectric layer, and electrically connecting with the circuit layer at the same side; a high dielectric constant material layer embedded on the inside of the surface with the first electrode plate disposed on the outside thereof of the dielectric layer, and plastering the first electrode plate; and a second electrode plate disposed in the inner space of the dielectric layer, plastered with the high dielectric constant material layer, parallel with the first electrode plate, and electrically connecting to the circuit layer but not electrically connecting to the first electrode plate through the circuit layer.

2. The method as claimed in claim 1 , further comprising: forming a first conductive through hole penetrating the first, the second, and the third core layers to electrically connect the circuit layers of the first, the second, and the third core layers, while forming the circuit layers of the second core layer and the third core layer.

3. The method as claimed in claim 1 , further comprising: forming a second conductive through hole penetrating the first core layer to electrically connect the circuit layers on the two sides of the first core layer, while forming the circuit layers of the first core layer; and

forming a plurality of conductive vias in the dielectric layers of the second, and third core layers to electrically connect the circuit layers of the second core layer and the third core layer with the circuit layers on the two sides of the first core layer, respectively, while forming the circuit layers of the second core layer and the third core layer.

4. The method as claimed in claim 1 , further comprising: forming built-up structures on the two sides of the core structure, wherein the built-up structures individually comprise at least one dielectric layer, at least one circuit layer, a plurality of conductive vias, and a plurality of conductive pads; parts of the conductive pads electrically connect to the second, and third core layers, respectively; and the built-up structures further individually comprise a solder mask having a plurality of openings to expose the conductive pads.

5. The method as claimed in claim 1 , wherein all of the capacitors are aligned with one another in the thickness direction.