Electronic ballast with integral shutdown timer

1. A gas discharge lamp ballast with an integral shutdown timer, the ballast comprising:

a) a circuit for receiving AC power;

b) a converter circuit for converting the AC power to DC power;

c) a square wave oscillator powered from the DC power;

d) a resonant circuit powered by the square wave oscillator for supplying power to at least one gas discharge lamp; and

e) a time-delay circuit configured to disable the square wave oscillator, without interrupting the DC power supplied to the oscillator, upon the passage of a predetermined period of time from power-up of the AC power.

2. The ballast of claim 1 , wherein:

a) the converter circuit is configured such that, upon AC power-down, DC power remains available for some time after AC power-down; and

b) the time-delay circuit has an on mode when adequate power is supplied to a power input node of the time-delay circuit; the time-delay circuit including, in the on mode of the time-delay circuit

i) an output node selectively having a shutdown output voltage for disabling the square wave oscillator, or a neutral output voltage that does not disable the square wave oscillator;

ii) a reset input node for causing the output node to have a neutral output voltage when a reset voltage is applied to the reset input node;

iii) the reset voltage being generated in response to power-down of the AC power without a delay that would be present if the reset voltage were generated in response to power-down of the DC power; and

iv) power to the power input node being supplied from said DC power, so that the time-delay circuit reliably remains in the on mode when the reset voltage is applied to the reset input node.

3. The ballast of claim 1 , wherein:

a) the time-delay circuit comprises a resistive-capacitive circuit whose resistive and capacitance values determine a part or all of said predetermined period of time when said resistive-capacitive circuit is enabled;

b) the time-delay circuit generates a shut-down signal for shutting down the square wave oscillator upon elapse of said predetermined period of time; and

c) the resistive-capacitive circuit is disabled upon elapse of said predetermined period of time.

4. The ballast of claim 1 , wherein the time-delay circuit comprises:

a) a timing oscillator establishing a first period of time; and

b) a frequency divider responsive to the timing oscillator for dividing the frequency corresponding to the first period of time into a frequency corresponding to a second period of time;

c) the predetermined period of time being the same or greater than the second period of time.

5. The ballast of claim 4 , wherein the timing oscillator comprises a resistive-capacitive circuit whose resistive and capacitance values determine the first period of time.

6. The ballast of claim 1 , wherein:

a) the time-delay circuit comprises a resistive-capacitive circuit whose resistive and capacitive values determine a part of all of said predetermined period of time when voltage is applied to said resistive-capacitive circuit;

b) a first period of time being determined by the time required for capacitance of the resistive-capacitive circuit to reach a threshold level; the predetermined period of time being the same or greater than the first period of time.

7. The ballast of claim 1 , wherein the time-delay circuit has an on mode when adequate power is supplied to a power input node of the time-delay circuit; the time-delay circuit including, in the on mode of the time-delay circuit:

a) an output node selectively having a shutdown output voltage for disabling the square wave oscillator, or a neutral output voltage that does not disable the square wave oscillator;

b) a reset input node for causing the output node to have a neutral output voltage when a reset voltage is applied to the reset input node;

c) the reset voltage being generated, not in response to AC voltage in said circuit for receiving AC power, but in response to a reset-voltage generating circuit that is responsive to a manual reset indication from a user.

8. The ballast of claim 1 , wherein the predetermined period of time is greater than 15 minutes.

9. The ballast of claim 1 , wherein:

a) the ballast includes a fault-detection circuit configured to shut down the square wave oscillator in the presence of a fault; and

b) the time-delay network shuts down the square wave oscillator via the fault-detection circuit.

10. The ballast of claim 1 , wherein the square wave oscillator is controlled by an oscillator control and drive circuit comprising an integrated control circuit.

11. The ballast of claim 10 , wherein the square wave oscillator comprises a pair of transistors serially connected to each other at a common node; the common node being alternately connected to a DC voltage or to an associated reference voltage by alternate switching on of the transistors; the transistors each having a control node.

12. The ballast of claim 1 , wherein all mentioned circuits are mounted directly or indirectly on the same printed-circuit board.

13. A gas discharge lamp ballast with an integral shutdown timer, comprising:

a) a circuit for receiving AC power;

b) a converter circuit for converting the AC power to DC power; the converter circuit being configured such that, upon AC power-down, DC power remains available for some time after AC power-down;

c) a self-resonant square wave oscillator powered from the DC power; the square wave oscillator comprising a pair of transistors serially connected to each other at a common node; the common node being alternately connected to a DC voltage or to an associated reference voltage by alternate switching on of the transistors; the transistors each having a control node;

d) a resonant circuit powered by the square wave oscillator for supplying power to at least one gas discharge lamp; and

e) a time-delay circuit configured to disable one of said transistors of the square wave oscillator, without interrupting the DC power supplied to the oscillator, upon the passage of a predetermined period of time from power-up of the AC power; said disabling occurring by clamping the control node of said one of said transistors to a value that prevents switching on of said transistor.

14. The ballast of claim 13 , wherein the time-delay circuit has an on mode when adequate power is supplied to a power input node of the time-delay circuit; the time-delay circuit including, in the on mode of the time-delay circuit:

a) an output node selectively having a shutdown output voltage for disabling the square wave oscillator, or a neutral output voltage that does not disable the square wave oscillator;

b) a reset input node for causing the output node to have a neutral output voltage when a reset voltage is applied to the reset input node;

c) the reset voltage being generated in response to power-down of the AC power without a delay that would be present if the reset voltage were generated in response to power-down of the DC power; and

d) power to the power input node being supplied from said DC power, so that the time-delay circuit reliably remains in the on mode when the reset voltage is applied to the reset input node.

15. The ballast of claim 13 , wherein:

a) the time-delay circuit comprises a resistive-capacitive circuit whose resistive and capacitance values determine a part or all of said predetermined period of time when said resistive-capacitive circuit is enabled;

b) the time-delay circuit generates a shut-down signal for shutting down the square wave oscillator upon elapse of said predetermined period of time; and

c) the resistive-capacitive circuit is disabled upon elapse of said predetermined period of time.

16. The ballast of claim 13 , wherein the time-delay circuit comprises:

a) a timing oscillator establishing a first period of time; and

b) a frequency divider responsive to the timing oscillator for dividing the frequency corresponding to the first period of time into a frequency corresponding to a second period of time;

c) the predetermined period of time being the same or greater than the second period of time.

17. The ballast of claim 16 , wherein the timing oscillator comprises a resistive-capacitive circuit whose resistive and capacitance values determine the first period of time.

18. The ballast of claim 13 , wherein:

a) the time-delay circuit comprises a resistive-capacitive circuit whose resistive and capacitive values determine a part of all of said predetermined period of time when voltage is applied to said resistive-capacitive circuit;

b) a first period of time being determined by the time required for capacitance of the resistive-capacitive circuit to reach a threshold level; the predetermined period of time being the same or greater than the first period of time.

19. The ballast of claim 13 , wherein the time-delay circuit has an on mode when adequate power is supplied to a power input node of the time-delay circuit; the time-delay circuit including, in the on mode of the time-delay circuit:

a) an output node selectively having a shutdown output voltage for disabling the square wave oscillator, or a neutral output voltage that does not disable the square wave oscillator;

b) a reset input node for causing the output node to have a neutral output voltage when a reset voltage is applied to the reset input node;

c) the reset voltage being generated, not in response to AC voltage in said circuit for receiving AC power, but in response to a reset-voltage generating circuit that is responsive to a manual reset indication from a user.

20. The ballast of claim 13 , wherein the predetermined period of time is greater than 15 minutes.

21. The ballast of claim 13 , wherein:

a) the ballast includes a fault-detection circuit configured to shut down the square wave oscillator in the presence of a fault; and

b) the time-delay network shuts down the square wave oscillator via the fault-detection circuit.

22. The ballast of claim 13 , wherein all mentioned circuits are mounted directly or indirectly on the same printed-circuit board.