Semiconductor device having a contact plug connecting to a silicide film formed on a diffusion region of a flash memory cell
View Patent ↗The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first impurity diffusion region and a second impurity diffusion region, which are formed at a distance from each other in the semiconductor substrate;
a third impurity diffusion region and a fourth impurity diffusion region, which are formed at a distance from each other in the semiconductor substrate, and which have impurity concentrations lower than those of the first and second impurity diffusion regions, and the third impurity diffusion region which is formed adjacently to the second impurity diffusion region;
a first thermal oxidation film formed on a part of the first impurity diffusion region and covering the second impurity diffusion region, and a second thermal oxidation film formed on the semiconductor substrate between the third and fourth impurity diffusion regions;
a flash memory cell including a floating gate formed of a first conductive film formed on the first thermal oxidation film, an intermediate insulating film, and a control gate formed of a second conductive film, and the first and second impurity diffusion regions are source/drain regions of the flash memory cell;
an insulating sidewall formed beside the floating gate;
a MOS transistor including a gate electrode formed on the second thermal oxidation film, and the third and fourth impurity diffusion regions are source/drain regions of the MOS transistor;
a first metal silicide layer formed on a second part of the first impurity diffusion region, a second metal silicide layer on the fourth impurity diffusion region, and a fourth metal silicide layer formed on the third impurity diffusion region;
an interlayer insulating film which covers the flash memory cell and the MOS transistor; and
a first conductive plug formed in the interlayer insulating film and reaching the first metal silicide layer,
wherein a part of an upper surface of the first thermal oxidation film contacts with the interlayer insulating film.
2. The semiconductor device according to claim 1 , wherein the gate electrode is formed of the first conductive film.
3. The semiconductor device according to claim 1 , wherein
the first to fourth impurity diffusion regions have the same conductive type, and
the MOS transistor functions as a selection transistor for the flash memory cell.
4. The semiconductor device according to claim 1 , wherein,
on an upper surface of the gate electrode in a portion other than a contact region, the intermediate insulating film and the second conductive film are formed in this order, and
a second conductive plug, which is electrically connected to the gate electrode, is formed in the interlayer insulating film.
5. The semiconductor device according to claim 4 , further comprising
a third metal silicide layer is formed also on the upper surface of the gate electrode in the contact region, wherein
the third metal silicide layer and the second conductive plug are connected.
6. The semiconductor device according to claim 1 , wherein
the first and second conductive films are formed of a polysilicon film, and the intermediate insulating film is formed of an ONO film.