SRAM split write control for a delay element
A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
1. A Static Random Access Memory (SRAM), comprising:
first and second bit lines for communicating data signals;
first and second word lines for communicating enable signals;
first, second, third, and fourth SRAM memory cells each including a delay component and an associated pair of feedback elements, the delay, in operation, increasing a response time of its associated pair of feedback elements an amount of time greater than a recovery time associated with a single event upset, wherein the response time is characterized by a switching time of an inverter in a pair of cross coupled inverters, and wherein the recovery time is characterized by an amount of time it takes for a radiation induced charge to dissipate, the first and second memory cells coupled to the first word line, the third and fourth memory cells coupled to the second word line, the first and third memory cells coupled to the first bit line, and the second and fourth memory cells coupled to the second bit line; and
first, second, third, and fourth write-word lines for communicating delay and bypass signals, the first write-word line coupled to the delay of the first memory cell, the second write-word line coupled to the delay of the second memory cell, the third write-word line coupled to the delay of the third memory cell, and the fourth write-word line coupled to the delay of the fourth memory cell.
2. The device as in claim 1 , wherein the enable signals and the data signals are used in combination to read from and write to each memory cell within the SRAM.
3. The device as in claim 1 , wherein, each memory cell within the SRAM receives the delay signal on its respective write-word line when it is not being written to, the delay signal increasing the response time of the associated pair of feedback elements it is communicated to.
4. The device as in claim 1 , wherein each write-word line transmits the bypass signal when its associated memory cell is to be written to, the bypass signal decreasing the response time of the associated memory cell.
5. The device as in claim 4 , wherein the decreased response time is less than the recovery time of the first memory cell.