Vertical spacer electrodes for variable-resistance material memories and vertical spacer variable-resistance material memory cells
View Patent ↗Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
1. A process comprising:
forming a dielectric mesa above a semiconductive substrate;
forming a bottom spacer electrode against the dielectric mesa;
forming an isolated variable-resistance material memory (VRMM) cell in contact with the bottom spacerelectrode, wherein a minor-axis surface of the bottom spacerelectrode forms an interface with the isolated variable-resistance material memory (VRMM) cell; and
forming a top electrode in contact with the VRMM cell.
2. The process of claim 1 , wherein forming the VRMM cell includes forming an isolated variable-resistance material memory (VRMM) cell in contact with the bottom spacerelectrode, wherein a minor-axis surface of the bottom spacerelectrode forms an interface with a contact pad.
3. The process of claim 1 , further including:
forming a plurality of gate stacks upon the semiconductive substrate;
coupling the semiconductive substrate to a plurality of contacts;
coupling at least some of the contacts each to one of a plurality of contact pads; and
forming the bottom spacer electrode in contact with one of the plurality of contact pads.
4. The process of claim 1 , further including coupling the VRMM cell to portions in the semiconductive substrate, the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region.
5. The process of claim 1 , further including coupling the VRMM cell to portions in the semiconductive substrate, the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region for a VRMM device.
6. A process comprising:
forming an isolated variable-resistance material memory (VRMM) spacer cell above a semiconductive substrate;
forming a first electrode electrically coupled between the VRMM spacer cell and the semiconductive substrate, wherein a minor-axis surface of the first electrode forms an interface with the isolated variable-resistance material memory (VRMM) cell; and
forming a second electrode in contact with the VRMM spacer cell and across from the first electrode.
7. The process of claim 6 , further including coupling the VRMM spacer cell to portions in the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region.
8. The process of claim 6 , further including coupling the VRMM spacer cell to portions in the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region for a VRMM device.
9. An apparatus comprising:
a bottom spacer electrode in contact with a contact pad that is disposed upon a semiconductive substrate;
an isolated variable-resistance material memory (VRMM) cell coupled to the bottom spacer electrode, wherein a minor-axis surface of the bottom spacerelectrode forms an interface with the isolated variable-resistance material memory (VRMM) cell; and
a top electrode coupled to the VRMM cell.
10. The apparatus of claim 9 , wherein the VRMM cell includes a bottom spacerelectrode, wherein a minor-axis surface of the bottom spacerelectrode forms an interface with the contact pad.
11. The apparatus of claim 9 , wherein a variable-resistance material is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.
12. The apparatus of claim 9 , wherein the VRMM cell includes contact with the bottom spacer electrode along a minor-axis dimension and along a major-axis dimension, and wherein the variable-resistance material is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.
13. The apparatus of claim 9 , wherein the VRMM cell is coupled to portions in the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region.
14. An apparatus comprising:
an isolated variable-resistance material memory (VRMM) cell coupled to a first electrode and a contact that is disposed upon a semiconductive substrate, wherein a minor-axis surface of the isolated variable-resistance material memory (VRMM) cell forms an interface with the first electrode; and
a second electrode coupled to the VRMM cell.
15. The apparatus of claim 14 , wherein a variable-resistance material is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.
16. The apparatus of claim 14 , wherein the VRMM spacer cell is coupled to portions in the semiconductive substrate including an n-channel periphery, a p-channel periphery, and an array region.