A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
1. A memory device connectable with a host apparatus and adapted to operate with power supplied from the host apparatus, comprising:
external terminals for connecting with the host apparatus;
a non-volatile memory chip capable of storing data;
an IC chip capable of storing data; and
a controller chip connected with the external terminals, the non-volatile memory chip and the IC chip, wherein:
the non-volatile memory chip, the IC chip and the controller chip are discrete chips,
responsive to a command from the host apparatus, the controller chip writes data inputted from the host apparatus into the non-volatile memory chip via the external terminals, and responsive to a command from the host apparatus, the controller chip transfers data read from the non-volatile memory chip to the host apparatus via the external terminals,
responsive to a command from the host apparatus, the controller chip requests the IC chip to do processing, and
the non-volatile memory chip is capable of storing data inputted from the host apparatus via the external terminals, and information necessary for operating the IC chip.
2. The memory device according to claim 1 , wherein
the information necessary for operating the IC chip includes at least one of a control parameter for controlling processing in the IC chip, environment setting information necessary for processing in the IC chip and a status of processing in the IC chip.
3. The memory device according to claim 2 , wherein
the controller chip requests the IC chip to do processing based on the control parameter in the non-volatile memory chip.
4. The memory device according to claim 2 , wherein
the processing of the IC chip controllable based on the control parameter includes at least one of an activation/inactivation process of the IC chip, a reset process of the IC chip and an environment setting process of the IC chip.
5. The memory device according to claim 2 , wherein
the processing of the IC chip controllable based on the control parameter includes at least one of a first initializing process and a second initializing process of the IC chip, the first initializing process being executed when power supply to the memory device is started, and the second initializing process being executed when an initializing command is inputted to the memory device.
6. The memory device according to claim 1 , wherein:
the non-volatile memory chip includes a first area accessible by the controller chip and a second area accessible by the host apparatus,
the information necessary for operating the IC chip is stored in the first area, and
the data inputted from the host apparatus via the external terminals are stored in the second area.
7. The memory device according to claim 1 , wherein
the non-volatile memory chip includes an area used as a buffer during processing in the IC chip.
8. The memory device according to claim 1 , wherein:
the IC chip includes a CPU, an ROM, an RAM and an EEPROM, and
the controller chip includes a CPU, a first interface control circuit for the external terminals, a second interface control circuit for the non-volatile memory chip and a third interface control circuit for the IC chip.
9. A memory device connectable with a host apparatus and adapted to operate with power supplied from the host apparatus, comprising:
external terminals for connecting with the host apparatus;
a non-volatile memory chip capable of storing data;
an IC chip capable of processing data; and
a controller chip connected with the external terminals, the non-volatile memory chip and the IC chip, wherein
the non-volatile memory chip, the IC chip and the controller chip are discrete chips,
responsive to a command from the host apparatus, the controller chip writes data inputted from the host apparatus into the non-volatile memory chip via the external terminals, and responsive to a command from the host apparatus, the controller chip transfers data read from the non-volatile memory chip to the host apparatus via the external terminals, and
the controller chip references information in the non-volatile memory chip when the IC chip is initialized.
10. The memory device according to claim 9 , wherein
an initializing process of the IC chip is executed in at least one of cases where power supply to the memory device is started and where an initializing command is inputted to the memory device.
11. A memory device connectable with a host apparatus and adapted to operate with power supplied from the host apparatus, comprising:
external terminals for connecting with the host apparatus;
a non-volatile memory chip capable of storing data;
an IC chip capable of processing data; and
a controller chip connected with the external terminals, the non-volatile memory chip and the IC chip, wherein:
the non-volatile memory chip, the IC chip and the controller chips are discrete chips,
responsive to a command from the host apparatus, the controller chip writes data inputted from the host apparatus into the non-volatile memory chip via the external terminals, and responsive to a command from the host apparatus, the controller chip transfers data read from the non-volatile memory chip to the host apparatus via the external terminals, and
wherein, when receiving a command containing an IC chip command from the host apparatus, with the command having a sector size in an FAT system, the controller chip accesses the IC chip, and, when receiving a response from the IC chip, the controller transmits a response containing an IC chip response to the host apparatus, with the response having a sector size in the FAT system.
12. The memory device according to claim 11 , wherein
the command containing the IC chip command includes at least one of a format identifier and an IC chip command length in front of the IC chip command, and includes dummy data behind the IC chip command.
13. The memory device according to claim 11 , wherein the response containing the IC chip response includes at least one of a format identifier and an IC chip command length in front of the IC chip response, and includes dummy data behind the IC chip response.
14. The memory device according to claim 11 , wherein
the IC chip command includes a header including a class, an instruction and a parameter.
15. The memory device according to claim 14 , wherein
the IC chip command includes at least one of an input data length, input data and an output data length instruction behind the header.
16. The memory device according to claim 11 , wherein
the IC chip response includes a status.
17. The memory device according to claim 16 , wherein
the IC chip response includes output data in front of the status.
18. The memory device according to claim 11 , wherein
the IC chip command and the IC chip response comply with ISO/IEC 7816 standard.
19. The memory device according to claim 11 , wherein
the sector size in the FAT system is 512 bytes.
20. A memory device connectable with a host apparatus and adapted to operate with power supplied from the host apparatus, comprising:
a non-volatile memory chip capable of storing data;
an IC chip capable of processing data; and
a controller chip connected with the external terminals, the non-volatile memory chip and the IC chip, wherein
the non-volatile memory chip, the IC chip and the controller chip are discrete chips,
responsive to a command from the host apparatus, the controller chip writes data inputted from the host apparatus into the non-volatile memory chip via the external terminals, and responsive to a command from the host apparatus, the controller chip transfers data read from the non-volatile memory chip to the host apparatus via the external terminals, and
when receiving a command of 512 bytes containing an IC chip command from the host apparatus, the controller chip accesses the IC chip, and, when receiving a response from the IC chip, the controller transmits a response of 512 bytes containing an IC chip response to the host apparatus.