DRAM architecture

1. A dynamic random access memory (DRAM), comprising:

a plurality of memory cells arranged into rows and columns,

wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column;

a differential amplifier adapted to amplify an input voltage difference (V P −V N ) between a pair of bit lines, wherein a first one of the bit lines is charged to the voltage V P and a second one of the bit lines is charged to the voltage V N , the differential amplifier amplifying the input voltage difference according to a gain G so as to drive an output voltage difference (V PO −V NO ) between a pair of output nodes, wherein a first one of the output nodes is charged to the voltage V PO and a second one of the output nodes is charged to the voltage V NO , the differential amplifier having a non-zero offset bias voltage (ΔV) such that if the input voltage difference is zero, the output voltage difference is non-zero; and

a self-bias generation circuit adapted to couple the first output node to the second bit line such that the output voltage V PO equals the input voltage V N and to couple the second output node to the first bit line such that the output voltage V NO equals the input voltage V P , the offset bias voltage ΔV thereby being reduced responsive to the gain G.

2. The DRAM of claim 1 , wherein the L-shaped memory cells in each column are arranged in pairs such that an end of a first L-shaped memory cell in each pair couples to an end of a remaining L-shaped memory cell in the pair in an end-to-end fashion such that each pair forms a C-shaped memory cell pair.

3. The DRAM of claim 2 , wherein the L-shaped memory cells in each pair couple to each other through a bit line contact.

4. The DRAM of claim 2 , wherein the C-shaped memory cell pairs in a first column face a first direction, the C-shaped memory cell pairs in an adjacent second column face an opposing second direction, and so on, such that the C-shaped memory cell pairs in neighboring columns face in opposite directions.

5. The DRAM of claim 4 , wherein the C-shaped memory pairs in a given column interlock with the C-shaped memory pairs in a neighboring column such that for a given C-shaped memory pair in a given column, an first and second end of two C-shaped memory pairs in a neighboring column fit between the ends of the given C-shaped memory pair.

6. The DRAM of claim 1 , wherein each row is crossed by a plurality of word lines.

7. The DRAM of claim 6 , wherein the plurality of word lines is four.

8. The DRAM of claim 7 , wherein each column corresponds with a bit line, the DRAM further comprising:

a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and

a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.

9. The DRAM of claim 8 , wherein each row of four word lines is arranged into two pairs such that a first pair of word lines in each row couples to a first word line driver through a first semiconductor process metal layer and a remaining pair of word lines in each row couples to a second word line driver through a second semiconductor process metal layer, the second semiconductor process metal layer being separated from the first semiconductor process layer by at least one insulating layer.

10. The DRAM of claim 9 , further comprising a strapping transistor arranged such that the assertion of one of the word lines in one of the pairs will drive the strapping transistor to couple the remaining word line in the one pair to ground.

11. The DRAM of claim 1 , wherein each access transistor and storage transistor are thick-gate I/O devices.